Abstract: The present invention allows for the detection and correction of certain error conditions in packet-based data communications systems, including systems utilizing multiple channels or signal pairs, where all channels or signal pairs do not carry a link integrity signal or other repetitive non-data signal. A first aspect of the present invention provides detection and correction for reverse polarity. A second aspect of the present invention provides detection and correction for pair swap. A third aspect of the present invention provides a link integrity function. Detection of reverse polarity, detection of pair swap, and detection of link integrity utilizes the non-data components of received packets, either independently or in conjunction with a link integrity signal or other repetitive non-data signal. Reverse polarity is corrected by inverting the received signals prior to transmission or repetition to subsequent circuitry.

Abstract: A phase locked loop includes a differential charge pump to cancel static phase error and reduce sensitivity to noise. The differential charge pump comprises two substantially identical single-ended charge pumps so that under locked condition, changes in voltage at the charge pumps' output terminals are substantially identical, thereby maintaining a substantially constant difference between the charge pumps' output voltage. A differential input voltage-controlled oscillator receives the output of the differential charge pump and generates a clock signal with a frequency proportional to the voltage difference output by the differential charge pump. A common mode bias circuit adjusts the common mode voltage output by the differential charge pump to optimize the voltage swing available at the differential charge pump's output terminals.

Abstract: The present invention allows for the detection and correction of certain error conditions in packet-based data communications systems, including systems utilizing multiple channels or signal pairs, where all channels or signal pairs do not carry a link integrity signal or other repetitive non-data signal. A first aspect of the present invention provides detection and correction for reverse polarity. A second aspect of the present invention provides detection and correction for pair swap. A third aspect of the present invention provides a link integrity function. Detection of reverse polarity, detection of pair swap, and detection of link integrity by utilizes the non-data components of received packets, either independently or in conjunction with a link integrity signal or other repetitive non-data signal. Reverse polarity is corrected by inverting the received signals prior to transmission or repetition to subsequent circuitry.

Abstract: A transceiver module for coupling between cells in a distributed intelligence network and a twisted pair line. The module receives power from the line and provides power to its respective cell. At the end of transmitting a packet, the transceiver transmits a code violation, then an anti-code violation to dissipate energy in the line. This is followed by clamping the line for the dead time between packets. N transceivers may be connected (without a cell) to form a repeater. The transceiver module may be used in a network having free topology; that is, an ideal transmission line, with terminators is not needed.

Abstract: A transceiver for transmitting and receiving digital data represented as stair-stepped sinusoidal waveforms over twisted pair lines interconnecting nodes of a network. The transmitter of the transceiver converts square waves into the stair stepped sinusoidal waveforms by utilizing a number of current sources for supplying differing amounts of current to a resistor coupled across the twisted pair lines. Shift registers control a set of switches which control the direction and the amount of current flowing through the resistor. Thereby, the output voltage across the resistor can be controlled to produce the stair-stepped sinusoidal waveform by clocking the digital signal to the shift registers. The receiver of the transceiver re-converts received stair-stepped sinusoidal waveforms back to their respective digital signals.

Abstract: A transceiver module for coupling between cells in a distributed intelligence network and a twisted pair line. The module receives power from the line and provides power to its respective cell. At the end of transmitting a packet, the transceiver transmits a code violation (pulse), then an anti-code violation (pulse of opposite polarity) to dissipate energy in the line. This is followed by clamping the line for the dead time between packets. N transceivers may be connected (without a cell) to form a repeater. The transceiver module may be used in a network having free topology; that is, an ideal transmission line, with terminators is not needed.

Abstract: A digital logic buffer device for generating dual polarity analog signals is described. In the presently preferred embodiment, buffer receives the positive polarity analog output of a digital-to-analog converter (V.sub.DAC), and a sign bit. If the sign bit indicates that a positive polarity is required, the buffer will output approximately V.sub.DAC. If a negative polarity is required, aproximately -V.sub.DAC will be generated.

Abstract: An integrated circuit processor real time processing of analog signals is described. The programmable processor duplicates filters, waveform generators and non-linear functions, such as rectification, with a high degree of stability and at a relatively low cost. A two-port, random-access memory provides inputs to an arithmetic logic unit (ALU). One of these inputs is coupled through a scaler (shifter). This scaler in conjunction with the ALU provides efficient multiplication, particularly by coefficients. ALU overflows are handled in an unusual manner to eliminate additional processing time for overflows. In a typical application, the one chip processor, with its 192-word program, samples an input analog signal at the rate of 13,020 Hz and detects the 8 tones used in telephony.

Abstract: An improved dynamic MOS RAM employing capacitive storage memory cells having a single active device per cell. The RAM includes several improved circuits and techniques which reduce power consumption and pattern sensitivity and which also provide a higher speed memory. Complementary input/output lines are employed which are coupled to alternate pair of the bit-sense lines making the use of a bistable output latch and push-pull output buffer more advantageous. The sense amplifiers associated with each of the bit lines are activated by a dual sloped signal to reduce noise and increase sensitivity and gain in the amplifiers. The output lines of the address buffers are initially "high" and then brought to their final level after an address is received by the buffers.