Patents by Inventor Stephen F. Moore

Stephen F. Moore has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6904518
    Abstract: The most or least significant bit of a datum can bet determined using parallel operations. This may result in faster location of the most or least significant bit without necessarily introducing more overhead in some embodiments.
    Type: Grant
    Filed: July 25, 2002
    Date of Patent: June 7, 2005
    Assignee: Intel Corporation
    Inventor: Stephen F. Moore
  • Publication number: 20040096057
    Abstract: A technique for modular multiplication of multi-precision numbers involves providing a table of pre-computed residues and reducing a large modular product to smaller modular equivalent using the table.
    Type: Application
    Filed: November 20, 2002
    Publication date: May 20, 2004
    Inventor: Stephen F. Moore
  • Publication number: 20040098435
    Abstract: A technique for modular reduction of multi-precision numbers involves providing a table of pre-computed residues and reducing a large number to smaller modular equivalent using the table.
    Type: Application
    Filed: November 20, 2002
    Publication date: May 20, 2004
    Inventor: Stephen F. Moore
  • Publication number: 20040019769
    Abstract: The most or least significant bit of a datum can bet determined using parallel operations. This may result in faster location of the most or least significant bit without necessarily introducing more overhead in some embodiments.
    Type: Application
    Filed: July 25, 2002
    Publication date: January 29, 2004
    Inventor: Stephen F. Moore
  • Patent number: 6633896
    Abstract: The present invention provides a computer-implemented method for multiplying two large multiplicands. The method includes generating a plurality of partial products by multiplying each digit of the first multiplicand with each digit of the second multiplicand. The resulting partial products have a least significant digit and a most significant digit. The method further includes adding each of the most significant digits to a first array and adding each of the least significant digits to a second array. The method then includes adding the first array to the second array, wherein the result is the product of the two original multiplicands.
    Type: Grant
    Filed: March 30, 2000
    Date of Patent: October 14, 2003
    Assignee: Intel Corporation
    Inventors: Stephen F. Moore, Seth Abraham
  • Patent number: 6116845
    Abstract: Articulating workpiece transfer apparatus comprises a pair of identical housings each of which has a circular flange projecting from one side of the housing and abutting one another. Each flange has adjacent its periphery a beveled edge. A circular clamp has a concave groove in which the peripheral edges of the flanges are accommodated, and such clamp is operable to apply a clamping force on each flange urging the latter into face-to-face engagement with one another. Each housing has a cylindrical opening for the accommodation of an elongate transfer arm which is linearly slideable and rotatable about the axis of the arm. Each housing includes a clamp which enables and disables relative movement between the associated arm and the housing. The housings are rotatable relative to each other about an axis which passes through both flanges and which is normal to the axis of rotation of the respective transfer arms.
    Type: Grant
    Filed: March 19, 1998
    Date of Patent: September 12, 2000
    Assignee: Atlas Technologies, Inc.
    Inventors: Joseph M. Wright, James H. Niedzielski, Stephen F. Moore
  • Patent number: 5528503
    Abstract: An integrated automation development system (10) for controlling and coordinating manufacturing equipment (24) employs a plurality of server processes (14, 16, 22, 28, 34, 36). Each server process includes a messaging manager (45) for receiving ASCII messages, and an interpreter (43) for evaluating the received ASCII messages and identifying commands within the messages. The server process further includes a command manager (41) for receiving and executing the commands, and a logic controller (47) for managing the logic flow of the command execution by the command manager (41). The servers may include additional commands (48) that enable them to serve as queue servers (34), terminal servers (28), and other application-specific server processes.
    Type: Grant
    Filed: April 30, 1993
    Date of Patent: June 18, 1996
    Assignee: Texas Instruments Incoporated
    Inventors: Stephen F. Moore, Thomas E. Byrd