Abstract: Method, receiver and computer program product for decoding a coded data block received at the receiver are disclosed. A first plurality of coded data bits representing the coded data block are received. First soft information values are determined corresponding to respective ones of the received first plurality of coded data bits, wherein each of the soft information values indicates a likelihood of a corresponding coded data bit having a particular value. An attempt is made to decode the coded data block using the first soft information values. The first soft information values are compressed. The compressed first soft information values are stored in a data store. A second plurality of coded data bits representing the coded data block is received and second soft information values corresponding to respective ones of the received second plurality of coded data bits are determined. The compressed first soft information values are retrieved from the data store and decompressed.

Abstract: A voltage margin controller, an IC included the same and a method of controlling voltage margin for a voltage domain of an IC are disclosed herein. In one embodiment, the voltage margin controller includes: (1) monitoring branches including circuit function indicators configured to indicate whether circuitry in the voltage domain could operate at corresponding candidate reduced voltage levels and (2) a voltage margin adjuster coupled to the monitoring branches and configured to develop a voltage margin adjustment for a voltage regulator of the voltage domain based upon an operating number of the circuit function indicators.

Abstract: A degradation detector for an integrated circuit (IC), a method of detecting aging in an IC and an IC incorporating the degradation detector or the method. In one embodiment, the degradation detector includes: (1) an offline ring oscillator (RO) coupled to a power gate and a clock gate, (2) a frozen RO coupled to a clock gate, (3) an online RO and (4) an analyzer coupled to the offline RO, the frozen RO and the online RO and operable to place the degradation detector in a normal state in which the offline RO is disconnected from both the drive voltage source and the clock source, the frozen RO is connected to the drive voltage source but disconnected from the clock source and the online RO is connected to both the drive voltage source and the clock source.

Abstract: A voltage margin controller, an IC included the same and a method of controlling voltage margin for a voltage domain of an IC are disclosed herein. In one embodiment, the voltage margin controller includes: (1) monitoring branches including circuit function indicators configured to indicate whether circuitry in the voltage domain could operate at corresponding candidate reduced voltage levels and (2) a voltage margin adjuster coupled to the monitoring branches and configured to develop a voltage margin adjustment for a voltage regulator of the voltage domain based upon an operating number of the circuit function indicators.

Abstract: A method and a system are provided for performing memory access assist using voltage boost. A memory access request is received at a storage cell array that comprises two or more subarrays, each subarray including at least one row of storage cells. The voltage boost is applied, during the memory access, to a first negative supply voltage of a first storage cell subarray of the two or more storage cell subarrays. The first negative supply voltage of the first storage cell subarray is lower than a second negative supply voltage of a second storage cell subarray of the two or more storage cell subarrays.

Abstract: Disclosed herein is a computer system operating on a local power supply of finite capacity has a plurality of system components each connected to a voltage supply system to draw current for their operation. The computer system includes a measuring circuit connected to detect prevailing usage of the local power supply, for example, a battery. The supply system is connected to receive an indication from the measuring circuit of excessive usage and is adapted to reduce the available supply voltage to selected ones of the system components. Each system component is associated with a clock controller which selects a clock frequency for operation of a component in dependence on the available voltage supply. Also disclosed is a supply system for a computer device operating on a local power supply of finite capacity.

Abstract: According to one aspect of the present disclosure, there is provided a flip flop circuit, comprising a first input circuit configured to receive a clock input signal and input data and comprising a first node. The flip-clop circuit further comprises a second input circuit configured to receive the input data and an inverse of the clock signal and comprising a second node. The first and second input circuits are configured such that the first node and the second node are pre-charged to respective complementary states when the clock signal is at a first level and, dependent on a value of the input data, one of said first and second nodes changes state to a state complementary to its pre-charged state when the clock signal transitions from the first level to a second level.

Abstract: An electrically powered mining vehicle including a frame rollingly supported on a surface for movement over the surface. An electric motor is coupled to the frame for proving power to the vehicle. A cable is electrically coupled to the electric motor for supplying electricity thereto and a cable management system is coupled to the frame and arranged to receive and payout the cable as the vehicle moves over the surface. A sheave bracket is coupled to the frame and arranged to direct the cable into the cable management system and includes a lower plate arranged substantially horizontally, a plurality of vertical rollers that are coupled to the lower plate and are arranged to guide the cable into the cable management system, and a horizontal roller that is coupled to the lower plate and arranged to elevate the cable above the lower plate.

Abstract: A system is based on an IC. A first component of the IC generates a signal that clocks the IC at a target operating frequency. A period corresponding to the target clock frequency exceeds a duration of a longest critical path associated with the IC. The first component and synchronous logic of the IC clocked therewith, each functions with the core supply voltage, which may be supplied to each via the same power supply rail. A second IC component detects errors that relate to an operation of the IC at the target clock frequency and determines a level for adjusting the core supply voltage. The Vdd adjustment ameliorates the frequency error. The voltage determination uses closed loop dynamic voltage and frequency scaling.

Abstract: An electrically powered mining vehicle including a frame rollingly supported on a surface for movement over the surface. An electric motor is coupled to the frame for proving power to the vehicle. A cable is electrically coupled to the electric motor for supplying electricity thereto and a cable management system is coupled to the frame and arranged to receive and payout the cable as the vehicle moves over the surface. A sheave bracket is coupled to the frame and arranged to direct the cable into the cable management system and includes a lower plate arranged substantially horizontally, a plurality of vertical rollers that are coupled to the lower plate and are arranged to guide the cable into the cable management system, and a horizontal roller that is coupled to the lower plate and arranged to elevate the cable above the lower plate.

Abstract: A processor including: a first and at least a second data processing channel with enable logic for selectively enabling the second channel; logic for generating first and second storage addresses having a variable offset therebetween based on the same one or more address operands of the same storage access instruction; and circuitry for transferring data between the first address and a register of the first data processing channel and between the second address and a corresponding register of the second channel based on a same one or more register specifier operands of the access instruction. The first data processing channel performs an operation using one or more registers of the first data processing channel, and on condition of being enabled the second channel performs the same operation using a corresponding one or more of its own registers based on the same one or more operands of the data processing instruction.

Abstract: A circuit for multiplying a digital signal by a variable gain, controlled in dependence on a digital gain control value. The circuit comprises: a multiplier input for receiving the digital signal; a multiplier output for outputting the digital signal multiplied by the gain; a plurality of multiplier stages each arranged to multiply by a respective predetermined multiplication factor; and switching circuitry arranged so as to apply selected ones of the multiplier stages in a multiplication path between the input and output, in dependence on the digital gain control value. The multiplication factors are arranged such that binary steps in the digital gain control value result in logarithmic steps in said gain.

Abstract: An integrated circuit is disclosed herein. In one embodiment, the integrated circuit includes: a processor; a plurality of external pins operatively coupled to the processor; and a permanently written memory operatively coupled to the processor, the memory having a plurality of regions each storing one or more respective boot properties for booting the processor. The processor is programmed to select one of the regions in dependence on an indication received via one or more of the external pins, to retrieve the one or more respective boot properties from the selected region, and to boot using the one or more retrieved boot properties.

Abstract: Method, receiver and computer program product for decoding a coded data block received at the receiver are disclosed. A first plurality of coded data bits representing the coded data block are received. First soft information values are determined corresponding to respective ones of the received first plurality of coded data bits, wherein each of the soft information values indicates a likelihood of a corresponding coded data bit having a particular value. An attempt is made to decode the coded data block using the first soft information values. The first soft information values are compressed. The compressed first soft information values are stored in a data store. A second plurality of coded data bits representing the coded data block is received and second soft information values corresponding to respective ones of the received second plurality of coded data bits are determined. The compressed first soft information values are retrieved from the data store and decompressed.

Abstract: An electrically powered mining vehicle including a frame rollingly supported on a surface for movement over the surface. An electric motor is coupled to the frame for proving power to the vehicle. A cable is electrically coupled to the electric motor for supplying electricity thereto and a cable management system is coupled to the frame and arranged to receive and payout the cable as the vehicle moves over the surface. A sheave bracket is coupled to the frame and arranged to direct the cable into the cable management system and includes a lower plate arranged substantially horizontally, a plurality of vertical rollers that are coupled to the lower plate and are arranged to guide the cable into the cable management system, and a horizontal roller that is coupled to the lower plate and arranged to elevate the cable above the lower plate.

Abstract: The invention provides a receiver comprising a data input and a strobe input. The strobe signal transitions whenever two consecutive bits in the data signal are the same. The receiver comprises combining means for generating a recovered clock signal from a combination of the data and strobe signals. The receiver also comprises a first sampling stage arranged to sample the data signal in dependence on the recovered clock signal, the first sampling stage comprising a plurality of sampling circuits and being arranged to obtain consecutive samples of the data signal using alternating ones of the sampling circuits. A second sampling stage is arranged to sample the data from the first sampling stage in dependence on a local system clock signal.

Abstract: A method for limiting peak-to-average power of a signal transmitted from a power amplifier. The method comprises: applying a pulse-shape filter to a first signal, thereby generating a second signal being a filtered version of the first signal; and outputting the second signal for transmission from a power amplifier. The method further comprises: applying each of a plurality of predictor filters to a respective instance of the first signal, each predictor filter approximating the application of the pulse-shape filter to the first signal based on a different respective set of filter coefficients, and each thereby generating a respective third signal. The method also further comprises determining an indicator of amplitude of each of the third signals, selecting the indicator corresponding to the largest of those amplitudes, generating a modifier based on the selected indicator, and using the modifier to limit the first signal prior to applying the pulse-shape filter.

Abstract: A processor including: a first and at least a second data processing channel with enable logic for selectively enabling the second channel; logic for generating first and second storage addresses having a variable offset therebetween based on the same one or more address operands of the same storage access instruction; and circuitry for transferring data between the first address and a register of the first data processing channel and between the second address and a corresponding register of the second channel based on a same one or more register specifier operands of the access instruction. The first data processing channel performs an operation using one or more registers of the first data processing channel, and on condition of being enabled the second channel performs the same operation using a corresponding one or more of its own registers based on the same one or more operands of the data processing instruction.

Abstract: A method for limiting peak-to-average power of a signal transmitted from a power amplifier. The method comprises: applying a pulse-shape filter to a first signal, thereby generating a second signal being a filtered version of the first signal; and outputting the second signal for transmission from a power amplifier. The method further comprises: applying each of a plurality of predictor filters to a respective instance of the first signal, each predictor filter approximating the application of the pulse-shape filter to the first signal based on a different respective set of filter coefficients, and each thereby generating a respective third signal. The method also further comprises determining an indicator of amplitude of each of the third signals, selecting the indicator corresponding to the largest of those amplitudes, generating a modifier based on the selected indicator, and using the modifier to limit the first signal prior to applying the pulse-shape filter.

Abstract: An integrated circuit is disclosed herein. In one embodiment, the integrated circuit includes: a processor; a plurality of external pins operatively coupled to the processor; and a permanently written memory operatively coupled to the processor, the memory having a plurality of regions each storing one or more respective boot properties for booting the processor. The processor is programmed to select one of the regions in dependence on an indication received via one or more of the external pins, to retrieve the one or more respective boot properties from the selected region, and to boot using the one or more retrieved boot properties.