Abstract: A virtual representation of a physical environment can be generated through simulation, which can include one or more virtual agents to represent robots, or at least semi-automated devices, that can operate and perform various tasks in the physical environment. Various component failures, or other potential problems, can be simulated that can be analyzed by one or more deep learning models associated with the virtual agents. These deep learning models can attempt to diagnose the simulated problem, as well as determine one or more potential solutions. The virtual agents can help to gather information for these determinations, as well as to perform tasks for these potential solutions. Once these deep learning models are trained in this simulated environment, these models can be used by one or more robots to perform tasks that may relate to maintenance or operation of a physical environment.

Abstract: A robot device determines an error associated with equipment included in a data center environment. The robot device may compare the error to candidate errors for which the robot device is already trained to resolve. Based on a result of the comparison, the robot device may perform, in a control environment, candidate maintenance operations in association with resolving the error. The robot device may learn a set of actions associated with successfully resolving the error, based on performing the candidate maintenance operations. The robot device may perform maintenance operations associated with the error. Performing the maintenance operations may include applying the learned set of actions.

Abstract: A printed circuit board assembly comprises: a printed circuit board (PCB); an integrated circuit (IC) package that is mounted on the PCB and includes a first surface and a bare IC die disposed on the first surface; and a vapor chamber coupled to the first surface of the IC package.

Abstract: A system comprises a first processing block configured to receive, from a first local resource, a formatted transaction in a format that is not recognizable by a remote endpoint; determine a first transaction category, from among a plurality of transaction categories, of the formatted transaction based on content of the formatted transaction; perform one or operations on the formatted transaction based on the first transaction category to form a reformatted transaction in a format that is recognizable by the remote endpoint; and place the reformatted transaction in a queue for transmission to the remote endpoint.

Abstract: A foreline for a vacuum pump with an inlet connectable to e.g. a vessel to be evacuated and an outlet connected to and inlet of the vacuum pump to evacuate the vessel. Thereby, the foreline further comprises a discharge line with a first end and a second end, wherein the first end comprises an opening and the second end comprises a solid material trap. The second end is arranged outside the foreline. The first end is arranged within the foreline between the inlet and the outlet and the opening is open towards the inlet of the foreline such that incoming solid material is collected by the opening, discharged through the discharge line and caught in the solid material trap.

Abstract: An imaging endoscopy system is disclosed, having a base unit, a hand controller, an umbilical section releasably connecting the base unit and the hand controller and an insertion section. The insertion section has a proximal end connected to the hand controller and a distal end for insertion into a subject, the distal end having a steering section and a distal tip. The hand controller includes at least one steering control for controlling bending of the steering section, and wherein the distal tip includes a light source for illumination of a region of tissue of interest and an imaging chip for imaging the region of tissue of interest. The hand controller, umbilical section and insertion section are single use disposable. The base unit is configured to be re-usable.

Abstract: A door hinge includes a door flange. The door flange includes a first-cylindrical portion. The first-cylindrical portion segmented and having an axially vectored borehole therethrough. The door hinge includes a frame flange. The frame flange including a second-cylindrical portion. The second-cylindrical portion segmented and having a corresponding axially vectored borehole therethrough. The first-cylindrical portion and second-cylindrical portion are configured to engage when their respective boreholes are coaxial. A plurality of apertures are disposed on the door flange and the frame flange. A plurality of plugs are included with the door hinge. Each of the plurality of plugs are sized and dimensioned to close at least one of the plurality of apertures. The door hinge is useful for attaching a door to a door frame.

Abstract: A fenestration assembly comprising a sliding glass assembly that slides between a fully closed position and a fully open position in which the sliding glass assembly is received into a pocket of the fenestration assembly. The pocket is covered on at least one side with insulation. The fenestration assembly may have two sliding glass assemblies. The fenestration assembly may be used in an energy efficient building system.

Abstract: A fenestration assembly comprising a sliding glass assembly that slides between a fully closed position and a fully open position in which the sliding glass assembly is received into a pocket of the fenestration assembly. The pocket is covered on at least one side with insulation. The fenestration assembly may have two sliding glass assemblies. The fenestration assembly may be used in an energy efficient building system.

Abstract: A fenestration assembly comprising a sliding glass assembly that slides between a fully closed position and a fully open position in which the sliding glass assembly is received into a pocket of the fenestration assembly. The pocket is covered on at least one side with insulation. The fenestration assembly may have two sliding glass assemblies. The fenestration assembly may be used in an energy efficient building system.

Abstract: A method and computer system for reducing the wiring congestion, required real estate, and access latency in a cache subsystem with a sectored and sliced lower cache by re-configuring sector-to-slice allocation and the lower cache addressing scheme. With this allocation, sectors having discontiguous addresses are placed within the same slice, and a reduced-wiring scheme is possible between two levels of lower caches based on this re-assignment of the addressable sectors within the cache slices. Additionally, the lower cache effective address tag is re-configured such that the address fields previously allocated to identifying the sector and the slice are switched relative to each other's location within the address tag. This re-allocation of the address bits enables direct slice addressing based on the indicated sector.

Abstract: In a multiprocessor environment, by executing cache-inhibited reads or writes to registers, a scan communication is used to rapidly access registers inside and outside a chip originating the command. Cumbersome locking of the memory location may be thus avoided. Setting of busy latches at the outset virtually eliminates the chance of collisions, and status bits are set to inform the requesting core processor that a command is done and free of error, if that is the case.

Abstract: In a cache coherent data processing system including at least first and second coherency domains, a memory block is stored in a system memory in association with a domain indicator indicating whether or not the memory block is cached, if at all, only within the first coherency domain. A master in the first coherency domain determines whether or not a scope of broadcast transmission of an operation should extend beyond the first coherency domain by reference to the domain indicator stored in the cache and then performs a broadcast of the operation within the cache coherent data processing system in accordance with the determination.

Abstract: In a cache coherent data processing system including at least first and second coherency domains, a master performs a first broadcast of an operation within the cache coherent data processing system that is limited in scope of transmission to the first coherency domain. The master receives a response of the first coherency domain to the first broadcast of the operation. If the response indicates the operation cannot be serviced in the first coherency domain alone, the master increases the scope of transmission by performing a second broadcast of the operation in both the first and second coherency domains. If the response indicates the operation can be serviced in the first coherency domain, the master refrains from performing the second broadcast.

Abstract: Illustrative embodiments disclose a data processing system providing low-level hardware access to in-band and out-of-band firmware. The data processing system includes a plurality of chips that includes at least one processor chip and a plurality of support chips. At least one processor chip includes a field replaceable unit support interface master that uses a field replaceable unit support interface serial transmission protocol to communicate with the plurality of support chips. Each one of the plurality of support chips includes a field replaceable unit support interface slave in, with ones of the plurality of chips that include a processor also include the field replaceable unit support interface master, and ones of the plurality of chips that do not include the processor include only the field replaceable unit support interface slave. Only the field replaceable unit support interface master possesses conversion logic.

Abstract: A cache memory logically partitions a cache array having a single access/command port into at least two slices, and uses a first directory to access the first array slice while using a second directory to access the second array slice, but accesses from the cache directories are managed using a single cache arbiter which controls the single access/command port. In one embodiment, each cache directory has its own directory arbiter to handle conflicting internal requests, and the directory arbiters communicate with the cache arbiter. The cache array is arranged with rows and columns of cache sectors wherein a cache line is spread across sectors in different rows and columns, with a portion of the given cache line being located in a first column having a first latency and another portion of the given cache line being located in a second column having a second latency greater than the first latency.

Abstract: A framed panel and related method of manufacture are disclosed. A framed panel unit includes a panel along the edge of which thermoplastic frame members are disposed. The frame members have first and second opposed side walls which define a channel for receiving the edge of the panel. The channel of each frame member has spacers between the panel and each side wall for spacing the panel from the side walls. Prior to welding together the ends of the frame members, the spacers retain the frame members on the panel. The panel may include multiple opposed sheet members with a spacer between the sheet members spacing them apart, and a reactive thermoplastic sealant material bonding the sheets to the frame members. An associated method of forming a named panel, frame members for a panel, and a spacer component for use in mounting a panel within a channel of a frame member are also disclosed.

Abstract: A method and apparatus are provided for a support interface for memory-mapped resources. A support processor sends a sequence of commands over and FSI interface to a memory-mapped support interface on a processor chip. The memory-mapped support interface updates memory, memory-mapped registers or memory-mapped resources. The interface uses fabric packet generation logic to generate a single command packet in a protocol for the coherency fabric which consists of an address, command and/or data. Fabric commands are converted to FSI protocol and forwarded to attached support chips to access the memory-mapped resource, and responses from the support chips are converted back to fabric response packets. Fabric snoop logic monitors the coherency fabric and decodes responses for packets previously sent by fabric packet generation logic. The fabric snoop logic updates status register and/or writes response data to a read data register. The system also reports any errors that are encountered.

Abstract: A method, system, and device for enabling intervention across same-level cache memories. In a preferred embodiment, responsive to a cache miss in a first cache memory a direct intervention request is sent from the first cache memory to a second cache memory requesting a direct intervention that satisfies the cache miss. In an alternate embodiment, direct intervention is utilized to access a same-level victim cache.

Abstract: A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit and a cache memory. The cache memory includes a cache controller, a data array including a data storage location for caching a memory block, and a cache directory. The cache directory includes a tag field for storing an address tag in association with the memory block and a coherency state field associated with the tag field and the data storage location. The coherency state field has a plurality of possible states including a state that indicates that the address tag is valid, that the storage location does not contain valid data, and that the memory block is possibly cached outside of the first coherency domain.