Abstract: A square-law clamping circuit (99, 120) sinks a current from an input/output terminal proportional to a square of a difference between a voltage thereon and a reference voltage. A first MOS transistor (130) has a source for receiving the reference voltage, a gate, and a drain coupled to its gate. A current source (134) coupled to the drain of the first MOS transistor (130) sources a predetermined current therefrom. A second MOS transistor (132) has a source providing the input/output terminal (100, 121), a gate coupled to the drain of the first MOS transistor (130), and a drain. A current sink (135) coupled to the drain of the second MOS transistor (132) sinks a current therefrom.

Abstract: A power-on reset circuit (30) for a memory (20) includes a DC model circuit (39), an N.sub.BIAS check circuit (64), and a NAND logic gate (71). A logic low power-on reset signal is provided at power-up of the memory (20) to establish initial conditions in a clock circuit (29) and in row and column predecoders/latches (24, 27). When the power supply voltage, a bandgap reference voltage, and a bias voltage all reach their predetermined voltages, the power-on reset circuit (30) provides a logic high power-on reset signal. In this manner, the power-on reset circuit (30) is assured of providing a logic low power-on reset signal until all of the proper voltage levels are reached. In addition, the power-on reset circuit models a DC circuit equivalent of an address buffer circuit (79) for compensating for process and temperature variations.

Abstract: A driver circuit (33) for output buffers or the like provides differing switching speed and di/dt depending on whether an output signal is switched in response to input signals or a control signal.

Abstract: A regulated BiCMOS output buffer (34) regulates a logic high voltage of an output signal to improve interfacing to loads such as 3.3 volt integrated circuits. The output buffer (34) provides a first voltage to a base of a pullup transistor (116) in response to a difference between an input voltage and a reference voltage. An emitter of the pullup transistor (116) provides an output signal. A second transistor (102) having characteristics matching those of the pullup transistor (116) receives the first voltage at its base, and provides the input voltage at its emitter. The output buffer (34) changes the first voltage until the voltage at the base of the second transistor (102) equals the reference voltage. Thus, signal reflections on the output signal do not affect the performance of the output buffer. Clamps (99, 120) coupled to the base and emitter of the pullup transistor (116) provide soft clamping according to a square law.