Abstract: A gate power control technique for a power amplifier (PA) provides practical improved efficiency at backed-off power levels. It can be applied to the main gate of the output stage of the PA, the cascode gate, or any combination thereof. Both voltage mode and current mode signal processing may be used. The gate power control can be implemented in both open-loop and closed-loop using AC and DC coupled drivers and output stages. It may further use one or more control ports in the radio frequency (RF) signal path.

Abstract: Power amplifier (PA), regardless of the process used for the manufacturing of its devices, suffers from a nonlinear output capacitance that has significant impact on various aspects of the PA performance. This output capacitance is dependent on the large output voltage swing. Accordingly a compensation capacitance is added at the output of the PA that has a behavior that is inverse respective of the output voltage of that of the output capacitance of the PA. Connecting the compensation capacitor in parallel to the PA output capacitance, results in a total capacitance that is the sum of the output capacitance and its compensation capacitance. The total output capacitance is therefore essentially stable throughout the output voltage swing.

Abstract: A power amplifier (PA) using switched-bulk biasing to minimize the risk of output stage snapback effect is disclosed. An adaptive biasing of the output stage prevents device breakdown while accommodating large voltage swings. These protection techniques can be applied to all types of cascode configurations of a PA, including single-ended, differential, quadrature, segmented and any combination thereto.

Abstract: Achievement of robust stability of a power amplifier (PA) that allows the sharing of the ground between the driver stages and the output stage is shown. A controlled amount of negative feedback is used to neutralize the local positive feedback that results from the driver-to-output stage ground sharing in the signal path, for example, a radio frequency (RF) signal path. The solution keeps a strong drive and a good performance of the PA. Exemplary embodiments are shown for the PA positive feedback neutralization. A first embodiment uses a ground signal divider while another embodiment uses a ground signal divider weighting technique.

Abstract: A power amplifier using a drain (collector) power control loop in which the feedback signal is an estimated output power level computed with a linear summation of the output sensed voltage and current. Both RF and baseband voltage and current sensing are possible, and voltage-mode or current-mode signal processing are feasible. This control loop technique is applicable to any means of drain power control circuits such as: supply regulators, DC-DC converters and others. Voltage error amplifiers can be used in conjunction with voltage feedback network, while current error amplifiers can be used with current feedback networks. Regulator sharing between different bands may be used as an area and cost reduction solution. The linear voltage and current summation driven power control technique can be also applied to the gate (base) power control scheme. Similarly, voltage-mode and current-mode signal processing can be implemented.

Abstract: Power amplifier (PA), regardless of the process used for the manufacturing of its devices, suffers from a nonlinear output capacitance that has significant impact on various aspects of the PA performance. This output capacitance is dependent on the large output voltage swing. Accordingly a compensation capacitance is added at the output of the PA that has a behavior that is inverse respective of the output voltage of that of the output capacitance of the PA. Connecting the compensation capacitor in parallel to the PA output capacitance, results in a total capacitance that is the sum of the output capacitance and its compensation capacitance. The total output capacitance is therefore essentially stable throughout the output voltage swing.

Abstract: A power amplifier (PA) using switched-bulk biasing to minimize the risk of output stage snapback effect is disclosed. An adaptive biasing of the output stage prevents device breakdown while accommodating large voltage swings. These protection techniques can be applied to all types of cascode configurations of a PA, including single-ended, differential, quadrature, segmented and any combination thereto.

Abstract: A gate power control technique for a power amplifier (PA) provides practical improved efficiency at backed-off power levels. It can be applied to the main gate of the output stage of the PA, the cascode gate, or any combination thereof. Both voltage mode and current mode signal processing may be used. The gate power control can be implemented in both open-loop and closed-loop using AC and DC coupled drivers and output stages. It may further use one or more control ports in the radio frequency (RF) signal path.

Abstract: Achievement of robust stability of a power amplifier (PA) that allows the sharing of the ground between the driver stages and the output stage is shown. A controlled amount of negative feedback is used to neutralize the local positive feedback that results from the driver-to-output stage ground sharing in the signal path, for example, a radio frequency (RF) signal path. The solution keeps a strong drive and a good performance of the PA. Exemplary embodiments are shown for the PA positive feedback neutralization. A first embodiment uses a ground signal divider while another embodiment uses a ground signal divider weighting technique.

Abstract: Various source follower circuits and methods for implementing such are disclosed. As one example, a class AB source follower circuit is disclosed that includes a source follower circuit that is actively biased. The dynamic biasing allows the source follower circuit to sustainably sink a DC current. In some instances of the embodiments, the class AB source follower circuits are operable to source and sink both AC and DC currents.

Abstract: A low voltage, high bandwidth, enhanced transconductance, source follower circuit constructed from MOS FET devices, which operates in a class AB mode. The drain current of the source follower is sensed with a folded cascode device. The sensed current is multiplied by a common source device of same type (NMOS or PMOS) as the source follower, and directed to the output load. Over limit current load at the source follower drain is sensed by a common source device of the opposite type (NMOS or PMOS), which also supplies the necessary extra current to the output load. This allows. the device to supply significantly more than the quiescent current in both sourcing and sinking the output. Average power consumption for driving a given load is significantly reduced, while maintaining the large bandwidth of traditional source follower designs, and the capability for use in either voltage regulators or in a current conveyor.

Abstract: A variable-gain amplifier (VGA), with one or more amplifier stages, has two or more offset correction sources connected to apply offset correction signals at different locations in the VGA. In one embodiment, each amplifier stage has both an input offset correction source and an output offset correction source. In another embodiment, each amplifier stage of a multi-stage VGA has an input offset correction source. By sequentially calibrating each amplifier stage, starting with the initial stage and proceeding downstream, the entire VGA can be calibrated to achieve gain-independent compensation for the adverse affects of input and output voltage offsets at the input and output, respectively, of each stage.

Abstract: An asymmetry-reducing circuit adapted to process an input signal having positive and negative pulses of different amplitudes and generate a corresponding balanced signal having positive and negative pulses of substantially uniform amplitudes. The asymmetry-reducing circuit balances the input signal by providing signal contributions corresponding to the second and third orders of the input signal. In a representative embodiment, the asymmetry-reducing circuit includes a differential amplifier and a plurality of arrayed MOS transistors connected to its inputs and outputs such that source-to-drain conductance of the transistors provides input and feedback resistances to the amplifier. A switch set selectively couples the fingers (gates) of the transistors to the input signal to modulate the source-to-drain conductance with said signal such that the input and feedback resistances change in a complementary manner.

Abstract: Variable-gain amplifiers (VGAs) and/or continuous-time filters (CTFS) are implemented with circuitry that provides improved power-supply rejection. The power-supply rejection circuitry may include a current source and a diode-connected MOSFET that inhibit noise in the reference-voltage power supply from reaching the output nodes of the VGA or CTF. Although the present invention enables separate implementations of VGAs and CTFs, in one embodiment, a VGA function and a CTF function are implemented in a single set of (e.g., integrated) circuitry.

Abstract: An AC coupling network has (a) a first pair of capacitances C1 connected between the input nodes and the output nodes and (b) a second pair of capacitances C2 cross-connected between the input nodes and the output nodes. The capacitances C1 and C2 are formed by sets of switched capacitors that can be configured to provide the network with different levels of attenuation while maintaining a constant AC coupling pole frequency. In particular, the sets of switched capacitors can be configured to ensure that C1+C2 remains constant, while C1?C2 varies. The present invention enables AC coupling to be implemented without using active devices such as operational amplifiers and/or buffers.

Abstract: A low voltage, high bandwidth, enhanced transconductance, source follower circuit constructed from MOS FET devices, which operates in a class AB mode. The drain current of the source follower is sensed with a folded cascode device. The sensed current is multiplied by a common source device of same type (NMOS or PMOS) as the source follower, and directed to the output load. Over limit current load at the source follower drain is sensed by a common source device of the opposite type (NMOS or PMOS), which also supplies the necessary extra current to the output load. This allows the device to supply significantly more than the quiescent current in both sourcing and sinking the output. Average power consumption for driving a given load is significantly reduced, while maintaining the large bandwidth of traditional source follower designs, and the capability for use in either voltage regulators or in a current conveyor.

Abstract: A voltage buffer and follower includes a single ended output, a source follower, and a current feedback loop. The current feedback loop is coupled to the source follower and to the single ended output. When two voltage followers are used in a differential configuration, the voltage followers can become part of a high bandwidth gain cell. The high bandwidth gain cell includes a first and a second source follower circuit that are coupled to the first and the second current feedback loops, respectively. The first and the second source follower circuits are further coupled to a first and a second current mirror circuit, respectively. The first and second current mirror circuits are coupled to a load, which is coupled to a common-mode feedback circuit. The common-mode feedback circuit controls a constant current source that sinks mirrored direct currents that flow through the first and the second current mirror circuits.

Abstract: A voltage buffer and follower includes a single ended output, a source follower, and a current feedback loop. The current feedback loop is coupled to the source follower and to the single ended output. When two voltage followers are used in a differential configuration, the voltage followers can become part of a high bandwidth gain cell. The high bandwidth gain cell includes a first and a second source follower circuit that are coupled to the first and the second current feedback loops, respectively. The first and the second source follower circuits are further coupled to a first and a second current mirror circuit, respectively. The first and second current mirror circuits are coupled to a load, which is coupled to a common-mode feedback circuit. The common-mode feedback circuit controls a constant current source that sinks mirrored direct currents that flow through the first and the second current mirror circuits.

Abstract: A method and apparatus for a variable gain amplifier has a well-regulated common mode output. The invention has particular applications to CMOS integrated circuits and has other applications. In a specific embodiment, the invention is used with a regulated voltage source that has good stability over a wide bandwidth of load changes.