Abstract: A computer memory apparatus is provided having a plurality of storage locations and a plurality of address decoder elements, each having a one or more input address connections for mapping to a respective one or more data elements of an input data entity. Decoding by a given one of the plurality of address decoder elements serves to conditionally activate the address decoder element depending on a function of values of the one or more data elements of the input data entity mapped to the one or more input address connection(s) and further depending on an activation threshold. Memory access operations to one of the plurality of storage locations are controlled by two or more distinct ones of the plurality of address decoder elements depending on coincidences in activation of the two or more distinct address decoder elements as a result of the decoding. A method and machine-readable instructions are also provided.

Abstract: A pulse circuit contains an input stage configured to receive input pulses on input nodes using push-pull elements, wherein a given push-pull element is configured to receive an input pulse on a given input node and to provide a corresponding internal signal. The pulse circuit further contains a feedback loop that includes a logic element coupled between outputs from the push-pull elements and reset nodes of the push-pull elements. This logic element is configured to provide one or more outputs from the pulse circuit and to reset the internal signals from the push-pull elements via the feedback loop.

Abstract: A memory configuration for use in a computer system, the memory comprising a plurality of address decoders each of which is allocated an identifier having a predetermined number of bits, each bit having first and second selectable states, and a data memory having a plurality of word lines of predetermined length, each of the said address decoders being activatable to select one of the plurality of word lines, and the address decoders comprising means to receive an input address having a predetermined number of bits and means to compare the identifier of an address decoder with the input address wherein the memory further comprises means to activate an address decoder if at least a predetermined minimum number of bits set to the first selectable state in the input address correspond to bits set to the first selectable state in the decoder identifier.