Patents by Inventor Stephen G. BENNETT

Stephen G. BENNETT has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8969200
    Abstract: An apparatus and method are provided for integrating TSVs into devices prior to device contacts processing. The apparatus includes a semiconducting layer; one or more CMOS devices mounted on a top surface of the semiconducting layer; one or more TSVs integrated into the semiconducting layer of the device wafer; at least one metal layer applied over the TSVs; and one or more bond pads mounted onto a top layer of the at least one metal layer, wherein the at least one metal layer is arranged to enable placement of the one or more bond pads at a specified location for bonding to a second device wafer. The method includes obtaining a wafer of semiconducting material, performing front end of line processing on the wafer; providing one or more TSVs in the wafer; performing middle of line processing on the wafer; and performing back end of line processing on the wafer.
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: March 3, 2015
    Assignee: The Research Foundation of State University of New York
    Inventors: Jeremiah Hebding, Megha Rao, Colin McDonough, Matthew Smalley, Douglas Duane Coolbaugh, Joseph Piccirillo, Jr., Stephen G. Bennett, Michael Liehr, Daniel Pascual
  • Publication number: 20130270711
    Abstract: An apparatus and method are provided for integrating TSVs into devices prior to device contacts processing. The apparatus includes a semiconducting layer; one or more CMOS devices mounted on a top surface of the semiconducting layer; one or more TSVs integrated into the semiconducting layer of the device wafer; at least one metal layer applied over the TSVs; and one or more bond pads mounted onto a top layer of the at least one metal layer, wherein the at least one metal layer is arranged to enable placement of the one or more bond pads at a specified location for bonding to a second device wafer. The method includes obtaining a wafer of semiconducting material, performing front end of line processing on the wafer; providing one or more TSVs in the wafer; performing middle of line processing on the wafer; and performing back end of line processing on the wafer.
    Type: Application
    Filed: April 12, 2012
    Publication date: October 17, 2013
    Applicant: The Research Foundation Of State University Of New York
    Inventors: Jeremiah HEBDING, Megha RAO, Colin McDONOUGH, Matthew SMALLEY, Douglas Duane COOLBAUGH, Joseph PICCIRILLO, JR., Stephen G. BENNETT, Michael LIEHR, Daniel PASCUAL