Abstract: This invention concerns real-time assembly of a compressed audio-visual system data stream (22) so the audio and video data may be subsequently presented in synchronism. Assembly of a system data stream (22) in accordance with present invention interleaves packets of data selected from a compressed audio bitstream (16) with packets of data selected from a compressed video bitstream (18). If frames of video data being assembled into the system data stream (22) advance too far ahead of the audio data being assembled into the system data stream (22), then all the data for a single frame of the video signal is omitted from the system data stream (22). Conversely, if frames of video data being assembled into the system data stream (22) lag too far behind the audio data being assembled into the system data stream (22), then a second copy of all the data for a single frame of the video signal is assembled into the system data stream (22).

Abstract: An instruction memory apparatus for a data processing unit stores a sequence of instructions. At each instruction fetch cycle, two sequentially adjacent instructions are accessed. An instruction preprocessing unit, coupled to the internal instruction memory, combines the two sequentially adjacent instructions into a single long instruction word when the two instructions meet predefined criteria for being combined. The first of the two instructions is combined with a no-operation instruction to generate a long instruction word when the predefined criteria are not met. In that case, the second instruction [may be accessed again] is used during the next instruction fetch cycle as the first of the two sequentially adjacent instructions to be processed during that next instruction fetch cycle.