Patents by Inventor Stephen G. Jamison

Stephen G. Jamison has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8575962
    Abstract: An integrated circuit comprises logic circuitry having a plurality of signal paths. A signal path of the plurality of signal paths has a propagation delay greater than a propagation delay of any other signal path of the plurality of signal paths. The signal path includes a plurality of components. The plurality of components is provided with a higher power supply voltage than any other signal path of the plurality of signal paths.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: November 5, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jianan Yang, Stephen G. Jamison, David L. Medlock, Gary Waugh
  • Patent number: 8446176
    Abstract: An integrated circuit ECO base cell module is formed with PMOS and NMOS gate electrode structures and power supply lines that are electrically separated from one another up to the second metal (M2) layer in a fixed circuit structure that may be reconfigured with one or more conductor elements formed above the M2 layer to form a predetermined circuit function.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: May 21, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jianan Yang, Darrin L. Hutchinson, Stephen G. Jamison
  • Publication number: 20130049807
    Abstract: An integrated circuit comprises logic circuitry having a plurality of signal paths. A signal path of the plurality of signal paths has a propagation delay greater than a propagation delay of any other signal path of the plurality of signal paths. The signal path includes a plurality of components. The plurality of components is provided with a higher power supply voltage than any other signal path of the plurality of signal paths.
    Type: Application
    Filed: August 29, 2011
    Publication date: February 28, 2013
    Inventors: JIANAN YANG, Stephen G. Jamison, David L. Medlock, Gary Waugh
  • Patent number: 7777522
    Abstract: First circuitry is powered by a first power supply domain and provides a data signal referenced to the first power supply domain. Second circuitry is powered by a second power supply domain that differs from the first power supply domain. The data signal becomes referenced to the second power supply domain by a clocked level shifter that couples the first circuitry to the second circuitry and buffers the data signal from the first power supply domain to the second power supply domain by only using a single supply voltage. The clocked level shifter is clocked by a signal that is used to precharge a first node and a second node of the clocked level shifter until the data signal is valid for at least a setup time period. The first and second nodes are precharged to establish a known state in the clocked level shifter.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: August 17, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jianan Yang, Wang K. Chen, Stephen G. Jamison
  • Publication number: 20100026343
    Abstract: First circuitry is powered by a first power supply domain and provides a data signal referenced to the first power supply domain. Second circuitry is powered by a second power supply domain that differs from the first power supply domain. The data signal becomes referenced to the second power supply domain by a clocked level shifter that couples the first circuitry to the second circuitry and buffers the data signal from the first power supply domain to the second power supply domain by only using a single supply voltage. The clocked level shifter is clocked by a signal that is used to precharge a first node and a second node of the clocked level shifter until the data signal is valid for at least a setup time period. The first and second nodes are precharged to establish a known state in the clocked level shifter.
    Type: Application
    Filed: July 31, 2008
    Publication date: February 4, 2010
    Inventors: Jianan Yang, Wang K. Chen, Stephen G. Jamison
  • Publication number: 20090302885
    Abstract: A circuit for body biasing is provided. The circuit includes: (1) a p-type transistor having a first current terminal, which is coupled to a first voltage supply, a second current terminal, a control terminal, and a bulk terminal; and (2) an n-type transistor having a first current terminal, which is coupled to a second voltage supply different from the first voltage supply, a second current terminal, a control terminal, and a bulk terminal, wherein the bulk terminal of the p-type transistor, the second current terminal of the p-type transistor, and the control terminal of the n-type transistor is coupled to a first node, wherein the control terminal of the p-type transistor, the bulk terminal of the n-type transistor, and the second current terminal of the second transistor is coupled to a second node different from the first node.
    Type: Application
    Filed: June 6, 2008
    Publication date: December 10, 2009
    Inventors: JIANAN YANG, Wang K. Chen, Stephen G. Jamison, Arthur R. Piejko, Jun Tang
  • Patent number: 6046897
    Abstract: A segmented bus architecture (800) removes certain ESD circuitry from each I/O pad cell (806, 812) and places it in a power pad cell (808, 814) or in some other unused area of the integrated circuit which incorporates the SBA. The removed ESD circuit is shared by several adjacent I/O pad cells via a segmented ESD bus. As a result, each individual I/O pad cell may be reduced in size.
    Type: Grant
    Filed: September 29, 1997
    Date of Patent: April 4, 2000
    Assignee: Motorola, Inc.
    Inventors: Jeremy C. Smith, Stephen G. Jamison
  • Patent number: 5917336
    Abstract: An electrostatic discharge (ESD) circuit (700) provides robust protection to an input/output driver circuit (10). The discharge path is provided by a bipolar transistor (202). The bipolar device is triggered by a combination of an n-type MOSFET (702), a string of diodes (200), and a biasing circuit (704). The trigger point of the MOSFET is programmable by varying the number of individual diodes in the string of diodes. The relatively high transconductance of the n-type MOSFET allows the use of a smaller ESD circuit for a given degree of protection.
    Type: Grant
    Filed: September 29, 1997
    Date of Patent: June 29, 1999
    Assignee: Motorola, Inc.
    Inventors: Jeremy C. Smith, Stephen G. Jamison
  • Patent number: 5814893
    Abstract: Bond pads (394, 106) and bond pad openings (62, 108) are formed such that the bond pad openings (62, 108) are asymmetric to the conductive sections (398, 106) of the bond pads (394, 106). If the bond pads are more likely to lift from the scribe line side of the bond pad (394, 106), the bond pad openings (62, 108) are formed such that the passivation layer (52) overlies more of the conductive section (398, 106) near the scribe line (40). If the bond pads (394, 106) are more likely to lift from the other side, the passivation layer (52) overlies more of the other side of the conductive section (398, 106). In addition to reducing the risk of lifting, contamination problems should also be reduced.
    Type: Grant
    Filed: February 13, 1997
    Date of Patent: September 29, 1998
    Assignee: Motorola Inc.
    Inventors: Ting-Chen Hsu, Edward O. Travis, Clifford M. Howard, Stephen G. Jamison
  • Patent number: 5773326
    Abstract: An SOI structure (20) includes a semiconductor layer (15) formed on an insulating substrate (12). The semiconductor layer (15) is partitioned into an ESD protection portion (32) and a circuitry portion (34). A portion of the semiconductor layer (15) in the ESD protection portion (32) and a different portion of the semiconductor layer (15) in the circuitry portion (34) are differentially thinned. A device (60) which implements the desired circuit functions of the SOI structure (20) is fabricated in the circuitry portion (34). An ESD protection device (40) is fabricated in the ESD protection portion (32). The thick semiconductor layer (15) in the ESD protection portion (32) serves to distribute the ESD current and heat over a large area, thereby improving the ability of the SOI structure (20) to withstand an ESD event.
    Type: Grant
    Filed: September 19, 1996
    Date of Patent: June 30, 1998
    Assignee: Motorola, Inc.
    Inventors: Percy V. Gilbert, Paul G. Y. Tsui, Stephen G. Jamison, James W. Miller
  • Patent number: 5744841
    Abstract: A semiconductor device with an electrostatic discharge (ESD) protection transistor is devised, wherein the ESD protection transistor has halo regions of an opposite conductivity type from the source and drain regions adjacent thereto. In one embodiment, the ESD protection transistor is a thick field oxide (TFO) transistor. In some cases, the halo regions may be provided with an ion implant step without the use of an extra mask. The halo regions permit the ESD protection transistor to have its breakdown voltage adjusted so that it turns on before the device it is protecting is affected by an ESD event. The use of halo regions avoids the increase in device area and adverse effects to the AC performance of the circuit being protected that are disadvantages of prior approaches.
    Type: Grant
    Filed: February 18, 1997
    Date of Patent: April 28, 1998
    Assignee: Motorola Inc.
    Inventors: Percy Veryon Gilbert, Paul G. Y. Tsui, Shih-Wei Sun, Stephen G. Jamison
  • Patent number: 5733794
    Abstract: A semiconductor device with an electrostatic discharge (ESD) protection transistor is devised, wherein the ESD protection transistor has halo regions of an opposite conductivity type from the source and drain regions adjacent thereto. In one embodiment, the ESD protection transistor is a thick field oxide (TFO) transistor. In some cases, the halo regions may be provided with an ion implant step without the use of an extra mask. The halo regions permit the ESD protection transistor to have its breakdown voltage adjusted so that it turns on before the device it is protecting is affected by an ESD event. The use of halo regions avoids the increase in device area and adverse effects to the AC performance of the circuit being protected that are disadvantages of prior approaches.
    Type: Grant
    Filed: February 6, 1995
    Date of Patent: March 31, 1998
    Assignee: Motorola, Inc.
    Inventors: Percy Veryon Gilbert, Paul G. Y. Tsui, Shih-Wei Sun, Stephen G. Jamison
  • Patent number: 5661082
    Abstract: Bond pads (394, 106) and bond pad openings (62, 108) are formed such that the bond pad openings (62, 108) are asymmetric to the conductive sections (398, 106) of the bond pads (394, 106). If the bond pads are more likely to lift from the scribe line side of the bond pad (394, 106), the bond pad openings (62, 108) are formed such that the passivation layer (52) overlies more of the conductive section (398, 106) near the scribe line (40). If the bond pads (394, 106) are more likely to lift from the other side, the passivation layer (52) overlies more of the other side of the conductive section (398, 106). In addition to reducing the risk of lifting, contamination problems should also be reduced.
    Type: Grant
    Filed: January 20, 1995
    Date of Patent: August 26, 1997
    Assignee: Motorola, Inc.
    Inventors: Ting-Chen Hsu, Edward O. Travis, Clifford M. Howard, Stephen G. Jamison