Patents by Inventor STEPHEN G. LUSKO
STEPHEN G. LUSKO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10754689Abstract: A stream manager for managing the distribution of instructions to a plurality of processing devices includes a dispatcher module configured to: receive multiple instruction streams, wherein each instruction stream includes a plurality of requested computations for processing perception data from a perception data source; partition each instruction stream into a plurality of partitions based on type of device to perform a requested computation from the instruction stream; assign a release time and deadline to each partition, and dispatch partition computations to a plurality of scheduling queues to distribute processing of the partition computations amongst the plurality of processing devices. The plurality of scheduling queues include: a plurality of CPU schedulers, wherein each CPU scheduler is assigned to a specific CPU and a specific scheduling queue; and a plurality of accelerator schedulers, wherein each accelerator scheduler is assigned to a specific scheduling queue and a specific type of accelerator.Type: GrantFiled: February 13, 2019Date of Patent: August 25, 2020Assignee: GM GLOBAL TECHNOLOGY OPERATIONS LLCInventors: Shige Wang, Unmesh Dutta Bordoloi, Stephen G. Lusko, Stephen N. McKinnie
-
Publication number: 20200257560Abstract: A stream manager for managing the distribution of instructions to a plurality of processing devices includes a dispatcher module configured to: receive multiple instruction streams, wherein each instruction stream includes a plurality of requested computations for processing perception data from a perception data source; partition each instruction stream into a plurality of partitions based on type of device to perform a requested computation from the instruction stream; assign a release time and deadline to each partition, and dispatch partition computations to a plurality of scheduling queues to distribute processing of the partition computations amongst the plurality of processing devices. The plurality of scheduling queues include: a plurality of CPU schedulers, wherein each CPU scheduler is assigned to a specific CPU and a specific scheduling queue; and a plurality of accelerator schedulers, wherein each accelerator scheduler is assigned to a specific scheduling queue and a specific type of accelerator.Type: ApplicationFiled: February 13, 2019Publication date: August 13, 2020Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLCInventors: Shige Wang, Unmesh Dutta Bordoloi, Stephen G. Lusko, Stephen N. McKinnie
-
Patent number: 10686988Abstract: Examples of techniques for dynamically selecting a batch size used in vehicle camera image processing are disclosed. In one example implementation, a method includes generating, by a processing device, a batch table and a mode table. The method further includes determining, by the processing device, image processing performance requirements for a current mode of a vehicle using the mode table, the vehicle comprising a plurality of cameras configured to capture a plurality of images. The method further includes selecting, by the processing device, a batch size and a processing frequency based at least in part on the image processing performance requirements for the current mode of the vehicle. The method further includes processing, by an accelerator, at least a subset of the plurality of images based at least in part on the batch size and processing frequency.Type: GrantFiled: April 11, 2018Date of Patent: June 16, 2020Assignee: GM GLOBAL TECHNOLOGY OPERATIONS LLCInventors: Unmesh Dutta Bordoloi, Shige Wang, Stephen G. Lusko, Jinsong Wang
-
Publication number: 20190320115Abstract: Examples of techniques for dynamically selecting a batch size used in vehicle camera image processing are disclosed. In one example implementation, a method includes generating, by a processing device, a batch table and a mode table. The method further includes determining, by the processing device, image processing performance requirements for a current mode of a vehicle using the mode table, the vehicle comprising a plurality of cameras configured to capture a plurality of images. The method further includes selecting, by the processing device, a batch size and a processing frequency based at least in part on the image processing performance requirements for the current mode of the vehicle. The method further includes processing, by an accelerator, at least a subset of the plurality of images based at least in part on the batch size and processing frequency.Type: ApplicationFiled: April 11, 2018Publication date: October 17, 2019Inventors: Unmesh Dutta Bordoloi, Shige Wang, Stephen G. Lusko, Jinsong Wang
-
Patent number: 10360079Abstract: A synchronization method in a multiprocessor system is provided. The method includes providing a plurality of synchronization mechanisms for synchronizing data to be accessed by a plurality of concurrently executable tasks, analyzing design information and runtime information for application software that includes the concurrently executable tasks, identifying, based on the analysis, software architecture patterns for the concurrently executable tasks that access a shared variable, and associating, based on the analysis, each of the software architecture patterns to one or more of the synchronization mechanisms.Type: GrantFiled: June 16, 2017Date of Patent: July 23, 2019Assignee: GM GLOBAL TECHNOLOGY OPERATIONS LLCInventors: Shige Wang, Stephen G. Lusko
-
Publication number: 20180365080Abstract: A synchronization method in a multiprocessor system is provided. The method includes providing a plurality of synchronization mechanisms for synchronizing data to be accessed by a plurality of concurrently executable tasks, analyzing design information and runtime information for application software that includes the concurrently executable tasks, identifying, based on the analysis, software architecture patterns for the concurrently executable tasks that access a shared variable, and associating, based on the analysis, each of the software architecture patterns to one or more of the synchronization mechanisms.Type: ApplicationFiled: June 16, 2017Publication date: December 20, 2018Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLCInventors: SHIGE WANG, STEPHEN G. LUSKO
-
Patent number: 9830270Abstract: A method of ordering memory access by an instruction cache of a central processing unit on a global memory device. A signal list of a link map file is extracted in the global memory device. Memory access traces relating to executed tasks are accessed from the signal list. Memory locations accessed in the global memory device from the access traces are identified. A correlation value for each pair of memory locations accessed in the global memory device is determined. Correlation values of the pairs of memory locations are determined, wherein the correlation values are computed based on a proximity of executable instructions utilizing the respective pair of memory locations. Accessed memory locations within the global memory device are reordered as a function of the determined correlation values. An executable file accessing the global memory device is modified.Type: GrantFiled: November 25, 2015Date of Patent: November 28, 2017Assignee: GM Global Technology Operations LLCInventors: Shuqing Zeng, Shige Wang, Stephen G. Lusko
-
Patent number: 9775035Abstract: A secure messaging communication system. A communication bus communicates messages between transmitting nodes. A secure hardware engine of a controller authenticates messages from requesting entities. A processor of the controller initially receives messages from the requesting entities. The processor includes a message request queue prioritizing received messages. The processor communicates a prioritized message from the request queue and associated authentication information to the secure hardware engine. The secure hardware engine authenticates the messages in response to receiving the prioritized messages and associated authentication information from the processor. The secure hardware engine communicates the authenticated messages to the processor for storage in a results queue.Type: GrantFiled: September 14, 2015Date of Patent: September 26, 2017Assignee: GM Global Technology Operations LLCInventors: Shige Wang, Stephen G. Lusko
-
Publication number: 20170147495Abstract: A method of ordering memory access by an instruction cache of a central processing unit on a global memory device. A signal list of a link map file is extracted in the global memory device. Memory access traces relating to executed tasks are accessed from the signal list. Memory locations accessed in the global memory device from the access traces are identified. A correlation value for each pair of memory locations accessed in the global memory device is determined. Correlation values of the pairs of memory locations are determined, wherein the correlation values are computed based on a proximity of executable instructions utilizing the respective pair of memory locations. Accessed memory locations within the global memory device are reordered as a function of the determined correlation values. An executable file accessing the global memory device is modified.Type: ApplicationFiled: November 25, 2015Publication date: May 25, 2017Inventors: SHUQING ZENG, SHIGE WANG, STEPHEN G. LUSKO
-
Publication number: 20170147402Abstract: A method of partitioning tasks on a multi-core ECU. A signal list of a link map file is extracted in a memory. Memory access traces relating to executed tasks are obtained from the ECU. A number of times each task accesses a memory location is identified. A correlation graph between the each task and each accessed memory location is generated. The correlation graph identifies a degree of linking relationship between each task and each memory location. The correlation graph is re-ordered so that the respective tasks and associated memory locations having greater degrees of linking relationships are adjacent to one another. The tasks are partitioned into a respective number of cores on the ECU. Allocating tasks and memory locations among the respective number of cores is performed as a function of substantially balancing workloads with minimum cross-core communication among the respective cores.Type: ApplicationFiled: November 25, 2015Publication date: May 25, 2017Inventors: SHUQING ZENG, SHIGE WANG, STEPHEN G. LUSKO
-
Publication number: 20170078878Abstract: A secure messaging communication system. A communication bus communicates messages between transmitting nodes. A secure hardware engine of a controller authenticates messages from requesting entities. A processor of the controller initially receives messages from the requesting entities. The processor includes a message request queue prioritizing received messages. The processor communicates a prioritized message from the request queue and associated authentication information to the secure hardware engine. The secure hardware engine authenticates the messages in response to receiving the prioritized messages and associated authentication information from the processor. The secure hardware engine communicates the authenticated messages to the processor for storage in a results queue.Type: ApplicationFiled: September 14, 2015Publication date: March 16, 2017Inventors: SHIGE WANG, STEPHEN G. LUSKO