Abstract: A fuse (43) is formed overlying a passivation layer (35) and under a packaging material (55, 70). In one embodiment, a fuse (43) is blown before the packaging material (55, 70) is formed. In some embodiments, the fuse (43) may be formed of metal (47), a metal nitride (42) or a combination thereof.

Abstract: An alignment aid for semiconductor devices. The alignment aid includes an area having a high level of reflectivity and an adjacent area having a of low level of reflectivity. The area having a low level of reflectivity includes at least one layer of tiles located in an interconnect layer of a semiconductor device and located over active circuitry of the semiconductor device. In some examples, the spacings between the tiles in a scan direction of the alignment aid is less than the wavelength of a light (e.g. a laser light) used to scan the alignment aid. In other examples, the width of the tiles in a scan direction of the alignment aid is less than the wave length of a laser used to scan the alignment aid.

Abstract: An alignment aid for semiconductor devices. The alignment aid includes an area having a high level of reflectivity and an adjacent area having a of low level of reflectivity. The area having a low level of reflectivity includes at least one layer of tiles located in an interconnect layer of a semiconductor device and located over active circuitry of the semiconductor device. In some examples, the spacings between the tiles in a scan direction of the alignment aid is less than the wavelength of a light (e.g. a laser light) used to scan the alignment aid. In other examples, the width of the tiles in a scan direction of the alignment aid is less than the wave length of a laser used to scan the alignment aid.

Abstract: A fuse (43) is formed overlying a passivation layer (35) and under a packaging material (55, 70). In one embodiment, a fuse (43) is blown before the packaging material (55, 70) is formed. In some embodiments, the fuse (43) may be formed of metal (47), a metal nitride (42) or a combination thereof.

Abstract: A semiconductor device substrate (600, 900) includes a semiconductor device (310, 314, 405, 424, 506, 912, 914, 918) and an alignment structure (508, 902) lying near the semiconductor device. The substrate (600, 900) includes a reflective layer (506, 510) and an antireflective layer (316, 926). The antireflective layer (316, 926) has a positional relationship with respect to the reflective layer (506, 510). The positional relationship is either such that the antireflective layer (316, 926) overlies all the reflective layer (506, 510) or such that none of the antireflective layer (316, 926) overlies the reflective layer (506, 510). The alignment structure (508, 902) includes an alignment feature (512), such as an alignment key.

Abstract: An alignment key (10) in a semiconductor substrate (40) is fabricated to display high optical contrast, and to prevent the diffusion of ionic contaminants through the alignment key (10) and into underlying portions of the semiconductor substrate (40). The alignment key (10) defines an enclosed structure formed by first and second metal layers (14, 20) which are electrically coupled by a filled via (22). A dielectric layer (42) is disposed between the metal layers (14, 20). A passivation layer (16) overlies an edge portion of the upper metal layer (14), however, the central portion of the upper metal layer (14) is bare. Slots (11, 12) in the upper metal layer (14) expose a portion of the lower layer (20) through the dielectric material (42). A high contrast scan signal (24) is generated as a continuous-wave laser beam traverses across the upper metal layer (14) and the slots (11,12).