Abstract: A receiver circuit (16) is programmable to operate with different logic family driver circuits (10). The receiver circuit has two external configuration pins (22,) 24) that are configured to provide the necessary termination for the type of logic family driver circuit used. To terminate the receiver circuit (16) for an ECL application will require first and second configuration pins (22,24) are connected to VCC—2 volts. To terminate the receiver circuit (16) for a CML application will require the first configuration pin (22) and the second configuration pin (24) are connected to VCC. LVDS termination for the receiver circuit (16) requires the first configuration pin (22) and the second configuration pin (24) are connected together. The configuration pins are external to a semiconductor package (14) housing the receiver circuit.

Abstract: A differential charge and dump optoelectronic receiver for baseband digital optoelectronic data links is disclosed having a preamplifier and a voltage controlled current source that defines the tail current of a differential pair functioning as a two quadrant multiplier, and using capacitors as loads on the differential pair making said differential pair an integrator. The integrator provides a full differential output, part of which is fedback to control the gain of the preamplifier. In a preferred embodiment, one integrator pair is used to recover the data from a Manchester encoded data stream. In another preferred embodiment, two pairs of integrators are used for QPSK like codes.

Abstract: A signal processing circuit (10) performs a sample and hold (16) of an input signal (14) and stores a maximum value of the input signal (18). A guardband signal (21) is developed that is less than the maximum value that is stored. The input signal is compared to the guardband signal to determine if the input signal is above or below the guardband signal. A threshold signal (25) is developed by taking a percentage of the maximum value that is stored. The input signal is compared to the threshold signal to regenerate the input waveform. If the input signal is below the guardband signal and above the threshold signal, the sample and hold circuit is reset to acquire a new maximum value of the input signal so that a new threshold can be used for regenerating the input signal.

Abstract: A signal processing circuit (10) generates a bias signal (27) that is used for biasing a comparator (26). An input signal (14) is compared to the bias signal (27) in order to reconstruct the input signal (14) on an output of the comparator. The bias signal (27) is generated by selecting the larger of a percent of the input signal (23) or an offset signal (24) that is larger than a minimum value of the input signal.

Abstract: A data transmitter (12) transmits parallel data as light pulses over multiple optical channels (14). A data receiver (16) converts the light pulses back to a voltage level and compares the voltage level to a reference capacitor voltage (42). The capacitor voltage should maintain a mid-range value for proper noise margin in detecting logic ones and logic zeroes. Any long series of consecutive logic ones or zeroes causes the capacitor voltage to charge or discharge toward the same level as the data voltage, which causes data errors. To prevent the data errors, the data is encoded (18) by inverting certain bits to break up the long series of consecutive logic states. The encoding information is transmitted as a transmitted clock to the data receiver over another fiber optic channel. The decoding information is retrieved (20) so that the encoded data can be converted back to proper logic states.