Abstract: The present invention provides a packing yarn that utilizes a non-metal woven reinforcement that provides lateral as well as longitudinal strength while improving the wear characteristics of the yarn material. To increase the support provided by the woven reinforcement, the yarn material and woven reinforcement are folded together such that the woven reinforcement is substantially coextensive with the yarn material in the resulting packing yarn.

Abstract: Liquid hydrocarbon storage tanks are cleaned by transferring the most contaminated lower fuel layer to an external vessel on a treatment truck where separation into a contaminants portion and a fuel portion occurs. The remnant fuel in the storage tank is cleaned by multiple passes through an external circuit on the truck. The fuel from the vessel is sometimes returned to the remnant fuel to be cleaned. The contaminants are discarded. The initial separation shortens the cleaning cycle. A flexible dip tube stiffened by a guide rod allows probing of the storage tank floor.

Abstract: The present invention relates to an improved quantum signal transmitter, which has a plurality of quantum output channels having at least one optical source and at least one optical splitter acting on the output of said at least one source.

Abstract: A system and method for a lottery game. The game includes a plurality of puzzles, where each puzzle is a concatenation of characters including letters, wherein some characters are missing from each puzzle. A player selects a set of characters from a predefined set of characters and if the select set of characters includes a solution for at least one puzzle, the player may receive a prize.

Abstract: A monitor-based Texas Hold'em Poker game, where a plurality of game entries are displayed to a player and each game entry is associated with a winning odds and potential payout. After the player places a wager on one of the game entries, the system generates a set of community cards and determines a winning hand according to a set of predefined rules.

Abstract: A method of treating a component made of a non magnetic alloy on which a magnetic surface layer has formed includes: (a) engaging a magnet of a calibrated magnet gauge with a surface of the component; (b) disengaging the magnet from the surface of the component and measuring a force required to disengage the magnet; (c) correlating the force with a thickness of the magnetic surface layer; and (d) if the thickness of the surface layer is greater than a predetermined minimum thickness, removing the surface layer.

Abstract: Processing engines (PE's) disposed on the substrate. Each processing engine includes a measurement and storage unit, and a PE controller coupled to each of the processing engines. The processing engines perform self-tests and store the results of the self-tests in the measurement and storage unit. The PE controller reads the results and selects a sub-set of processing engines based on the results and an optimization algorithm.

Abstract: Disclosed herein is a spray coating process for a robotic spray gun assembly comprising importing a discretized model of an object geometry to be coated; importing a numerically characterized spray pattern file; importing a robot motion file comprising a plurality of motion positions, dwell times and orientations defining a spray direction of the robotic spray gun; reading each motion position within the motion file; determining which portions of the object geometry are visible at each motion position; computing a void volume fraction at each visible portion of the object geometry based on the core compression, the incident angle of the robotic spray gun and the ricocheting of the spray for each motion position; and calculating total coating thickness on portions of the object geometry for the complete motion step.

Abstract: A design structure. The design structure includes: a first set of FETs having a designed first Vt and a second set of FETs having a designed second Vt, the first Vt different from the second Vt; a first monitor circuit containing at least one FET of the first set of FETs and a second monitor circuit containing at least one FET of the second set of FETs; a compare circuit configured to generate a compare signal based on a performance measurement of the first monitor circuit and of the second monitor circuit; a control unit responsive to the compare signal and configured to generate a control signal regulator based on the compare signal; and an adjustable voltage regulator responsive to the control signal and configured to voltage bias wells of FETs of the second set of FETs, the value of the voltage bias applied based on the control signal.

Abstract: A memory sub-system and a method for operating the same. The memory sub-system includes (a) a main memory, (b) an ECC circuit, (c) a hard fail identifier circuit, (d) a repair circuit, (e) a redundant memory, and (f) a threshold setting circuit. The ECC circuit is capable of (i) detecting a first bit fail, (ii) sending an error flag signal to the hard fail identifier circuit, (iii) sending a first location address, a first bit location of the first bit fail, and a repaired data from the first location address to the hard fail identifier circuit. The hard fail identifier circuit is capable of (i) determining the number of times of failure occurring at the first bit fail, (ii) determining whether the number of times of failure is equal to a predetermined threshold value, and (iii) if so, sending a threshold reached signal.

Abstract: A circuit and a method for adjusting the performance of an integrated circuit, the method includes: comprising: (a) measuring the performance of a first monitor circuit having at least one field effect transistor (FET) of a first set of FETs, each FET of the first set of FETs having a designed first threshold voltage; (b) measuring the performance of a second monitor circuit having at least one field effect transistor (FET) of a second set of FETs, each FET of the second set of FETs having a designed second threshold voltage, the second threshold voltage different from the first threshold voltage; and (c) applying a bias voltage to wells of the FETs of the second set of FETs based on comparing a measured performance of the first and second monitor circuits to specified performances of the first and second monitor circuits.

Abstract: A continuous process for purification of brine contaminated with alkaline earth metals. The process comprises combining the brine with an aqueous solution containing at least one of an alkali metal hydroxide and an alkali metal carbonate with efficient mixing by a micro-mixing device.

Abstract: Methods and apparatus to automatically link process control graphics to process control algorithm information are described. An example method involves displaying a first process control image including process control algorithm information and displaying adjacent to the first process control image a second process control image to include process control graphics. The method automatically links at least some of the process control algorithm information to a graphic in the second process control image in response to user inputs associated with the first and second process control images.

Abstract: A process for production of a borohydride compound. The process comprises combining a compound comprising boron and oxygen with an adduct of alane.

Abstract: Example methods and apparatus to bind properties in a process control system are disclosed. A disclosed example method involves associating a binding type with a property of a configuration element. A plurality of values for the property are then retrieved based on the plurality of values being associated with the binding type. At least some of the plurality of values are presented to a user. The example method also involves receiving a user-selected value from the at least some of the plurality of property values and generating a binding reference to bind the user-selected value to the configuration element.

Abstract: An explosive-resistant mine seal is provided, which includes a pair of block walls. An adhesive is provided between adjoining surfaces of the blocks where the adhesive has greater strength properties than the blocks themselves. A core member is provided between the two walls and is bound thereto. The adhesive may be coated over the walls to increase the strength of the mine seal.

Abstract: A circuit and a method for adjusting the performance of an integrated circuit, the circuit includes: first and second sets of FETs having respective first and second threshold voltages, the first threshold voltage different from the second threshold voltage; a first monitor circuit containing at least one FET of the first set of FETs and a second monitor circuit containing at least one FET of the second set of FETs; a compare circuit adapted to generate a compare signal based on a performance measurement of the first monitor circuit and a performance measurement of the second monitor circuit; and a control unit adapted to generate a control signal to a voltage regulator based on the compare signal, the voltage regulator adapted to supply a bias voltage to wells of FETs of the second set of FETs, the value of the bias voltage based on the control signal.

Abstract: A circuit and a method for adjusting the performance of an integrated circuit, the method includes: comprising: (a) measuring the performance of a first monitor circuit having at least one field effect transistor (FET) of a first set of FETs, each FET of the first set of FETs having a designed first threshold voltage; (b) measuring the performance of a second monitor circuit having at least one field effect transistor (FET) of a second set of FETs, each FET of the second set of FETs having a designed second threshold voltage, the second threshold voltage different from the first threshold voltage; and (c) applying a bias voltage to wells of the FETs of the second set of FETs based on comparing a measured performance of the first and second monitor circuits to specified performances of the first and second monitor circuits.

Abstract: A circuit and a method for adjusting the performance of an integrated circuit, the circuit includes: first and second sets of FETs having respective first and second threshold voltages, the first threshold voltage different from the second threshold voltage; a first monitor circuit containing at least one FET of the first set of FETs and a second monitor circuit containing at least one FET of the second set of FETs; a compare circuit configured to generate a compare signal based on a performance measurement of the first monitor circuit and a performance measurement of the second monitor circuit; and a control unit configured to generate a control signal to a voltage regulator based on the compare signal, the voltage regulator configured to supply a bias voltage to wells of FETs of the second set of FETs, the value of the bias voltage based on the control signal.

Abstract: A memory sub-system and a method for operating the same. The memory sub-system includes (a) a main memory, (b) an ECC circuit, (c) a hard fail identifier circuit, (d) a repair circuit, (e) a redundant memory, and (f) a threshold setting circuit. The ECC circuit is capable of (i) detecting a first bit fail, (ii) sending an error flag signal to the hard fail identifier circuit, (iii) sending a first location address, a first bit location of the first bit fail, and a repaired data from the first location address to the hard fail identifier circuit. The hard fail identifier circuit is capable of (i) determining the number of times of failure occurring at the first bit fail, (ii) determining whether the number of times of failure is equal to a predetermined threshold value, and (iii) if so, sending a threshold reached signal.