Abstract: A memory system for storing data is disclosed, the memory system including a plurality of memory devices configured to store data, each memory device having a plurality of bits, the memory devices configured and associated to work together as a rank to respond to a request; a memory control circuit associated with the plurality of memory devices and configured to output command and control signals to the plurality of memory devices; a detector for detecting a bit error in an operation; and a controller for remapping the bit error to a spare bit lane in response to the detector detecting the bit error.

Abstract: A memory system for storing data is disclosed, the memory system including a plurality of memory devices configured to store data, each memory device having a plurality of bits, the memory devices configured and associated to work together as a rank to respond to a request; a memory control circuit associated with the plurality of memory devices and configured to output command and control signals to the plurality of memory devices; a detector for detecting a bit error in an operation; and a controller for remapping the bit error to a spare bit lane in response to the detector detecting the bit error.

Abstract: A method and/or system for checking the bus/interface between a host and a memory system during memory access operations includes a memory system having one or more of the data memory devices and a spare memory device; providing a bus/interface between a host and the memory system; selecting information on a per memory device basis to associate with a spare memory device; disassociating the selected information from the one or more data memory devices and associating the selected information with the spare memory device; adding Cyclical Redundancy Check (CRC) code to the one or more data memory devices from which the selected information was disassociated; transferring the CRC code and information over the bus and interface between the host and the memory system; and checking the bus interface with the CRC code added to the one or more data memory devices.

Abstract: A method and/or system for checking the bus/interface between a host and a memory system during memory access operations includes a memory system having one or more of the data memory devices and a spare memory device; providing a bus/interface between a host and the memory system; selecting information on a per memory device basis to associate with a spare memory device; disassociating the selected information from the one or more data memory devices and associating the selected information with the spare memory device; adding Cyclical Redundancy Check (CRC) code to the one or more data memory devices from which the selected information was disassociated; transferring the CRC code and information over the bus and interface between the host and the memory system; and checking the bus interface with the CRC code added to the one or more data memory devices.

Abstract: A memory system for storing data is disclosed, the memory system including a plurality of memory devices configured to store data, each memory device having a plurality of bits, the memory devices configured and associated to work together as a rank to respond to a request; a memory control circuit associated with the plurality of memory devices and configured to output command and control signals to the plurality of memory devices; a detector for detecting a bit error in an operation; and a controller for remapping the bit error to a spare bit lane in response to the detector detecting the bit error.

Abstract: A method and/or system for checking the bus/interface between a host and a memory system during memory access operations includes a memory system having one or more of the data memory devices and a spare memory device; providing a bus/interface between a host and the memory system; selecting information on a per memory device basis to associate with a spare memory device; disassociating the selected information from the one or more data memory devices and associating the selected information with the spare memory device; adding Cyclical Redundancy Check (CRC) code to the one or more data memory devices from which the selected information was disassociated; transferring the CRC code and information over the bus and interface between the host and the memory system; and checking the bus interface with the CRC code added to the one or more data memory devices.

Abstract: A memory system for storing data is disclosed, the memory system including a plurality of memory devices configured to store data, each memory device having a plurality of bits, the memory devices configured and associated to work together as a rank to respond to a request; a memory control circuit associated with the plurality of memory devices and configured to output command and control signals to the plurality of memory devices; a detector for detecting a bit error in an operation; and a controller for remapping the bit error to a spare bit lane in response to the detector detecting the bit error.

Abstract: A method, computer system, and computer program product for self-correcting temperature and notification are provided. The embodiment may include detecting a user body temperature. The embodiment may also include determining if the detected body temperature is within a pre-configured normal temperature range. The embodiment may further include in response to the detected body temperature is outside the pre-configured threshold temperature range, adjusting the body temperature to the pre-configured normal temperature range. The embodiment may also include notifying a user when the detected body temperature reaches pre-configured dangerous body temperature.

Abstract: A computer-implemented method for calibrating DRAM is provided. A non-limiting example of the computer-implemented method includes reading, by a processor, system configuration information and disabling, by the processor, one or more steps in a list of calibration steps to be performed based on the system configuration information to leave a list of remaining calibration steps. Based on a determination that two or more remaining calibration steps are co-dependent, the method configures, by the processor, a single calibration step that encapsulates the co-dependent algorithm and places, by the processor, the single calibration step in a list of steps to be called. The method then provides, by the processor, the list of steps to be called.

Abstract: A computer-implemented method for calibrating DRAM is provided. A non-limiting example of the computer-implemented method includes reading, by a processor, system configuration information and disabling, by the processor, one or more steps in a list of calibration steps to be performed based on the system configuration information to leave a list of remaining calibration steps. Based on a determination that two or more remaining calibration steps are co-dependent, the method configures, by the processor, a single calibration step that encapsulates the co-dependent algorithm and places, by the processor, the single calibration step in a list of steps to be called. The method then provides, by the processor, the list of steps to be called.

Abstract: A memory system for storing data is disclosed, the memory system including a plurality of memory devices configured to store data, each memory device having a plurality of bits, the memory devices configured and associated to work together as a rank to respond to a request; a memory control circuit associated with the plurality of memory devices and configured to output command and control signals to the plurality of memory devices; a detector for detecting a bit error in an operation; and a controller for remapping the bit error to a spare bit lane in response to the detector detecting the bit error.

Abstract: A memory system for storing data is disclosed, the memory system including a plurality of memory devices configured to store data, each memory device having a plurality of bits, the memory devices configured and associated to work together as a rank to respond to a request; a memory control circuit associated with the plurality of memory devices and configured to output command and control signals to the plurality of memory devices; a detector for detecting a bit error in an operation; and a controller for remapping the bit error to a spare bit lane in response to the detector detecting the bit error.

Abstract: An aspect includes generating, within a first memory device of a memory system, a plurality of event-based information associated with activity in the memory system. The event-based information is stored in a reserved portion of the first memory device. The event-based information is provided to a memory controller of the memory system corresponding with an access of a memory row across a plurality of memory devices of the memory system associated with the event-based information.

Abstract: A double data rate (DDR) memory controller writes a test pattern to a location in a DDR memory for a coarse calibration test, delayed by a first number of cycles set in a tunable write delay setting. The DDR memory controller simulates a single data rate (SDR) mode for the coarse calibration test by only comparing every other read beat of the test pattern read from the DDR memory, delayed by a second number of cycles set in tunable read delay setting, wherein every other read beat is latched for a full cycle. The DDR memory controller, responsive to every other read beat of the test pattern matching an expected result, sets the first number of cycles and the second number of cycles as coarse calibration settings for a DRAM.

Abstract: A memory system for storing data is disclosed, the memory system including a plurality of memory devices configured to store data, each memory device having a plurality of bits, the memory devices configured and associated to work together as a rank to respond to a request; a memory control circuit associated with the plurality of memory devices and configured to output command and control signals to the plurality of memory devices; a detector for detecting a bit error in an operation; and a controller for remapping the bit error to a spare bit lane in response to the detector detecting the bit error.

Abstract: A double data rate (DDR) memory controller writes a test pattern to a location in a DDR memory for a coarse calibration test, delayed by a first number of cycles set in a tunable write delay setting. The DDR memory controller simulates a single data rate (SDR) mode for the coarse calibration test by only comparing every other read beat of the test pattern read from the DDR memory, delayed by a second number of cycles set in tunable read delay setting, wherein every other read beat is latched for a full cycle. The DDR memory controller, responsive to every other read beat of the test pattern matching an expected result, sets the first number of cycles and the second number of cycles as coarse calibration settings for a DRAM.

Abstract: An aspect includes generating, within a first memory device of a memory system, a plurality of event-based information associated with activity in the memory system. The event-based information is stored in a reserved portion of the first memory device. The event-based information is provided to a memory controller of the memory system corresponding with an access of a memory row across a plurality of memory devices of the memory system associated with the event-based information.

Abstract: A copper infiltrated ferrous powder metal part infiltrated with copper or a copper alloy characterized as having after infiltration a residual uninfiltrated porosity of less than about 7 volume percent and a maximum pore size of the residual uninfiltrated porosity of less than about 125 micrometers, said porosity and pore size values being taken from a worst field of view in a functionally critical area of said metal part.