Abstract: A storage device provides thin provisioning by presenting more logical capacity than available physical capacity. The storage device uses a dynamic random-access memory (DRAM) having a size that is proportional to the available physical capacity of the storage device. The storage device includes a memory device with a physical capacity and the DRAM. A controller on the storage device creates segments including logical block address (LBA) sets in an LBA space. The LBA sets include an LBA from each segment that are linked to enable the LBAs in a LBA set to share a mapping space in the DRAM. The controller also creates an L2P table including a LBA set entry per LBA set, with each LBA set entry including sub-entries to store physical locations on the memory device that are associated with the LBAs in the LBA set. The controller also stores the L2P table in the DRAM.

Abstract: A Controller Memory Buffer (CMB) caching mechanism can be used for increased CMB performance. Rather than reading data and writing data from the static random access memory (SRAM), data is read from the SRAM. When data is read from the CMB in SRAM there is increase performance, but little space to process both read and write commands. Using a dynamic random access memory (DRAM) for write commands and CMB in SRAM for read commands allows for increased performance. Due to limited space in the SRAM, when the read commands are read from the host, the commands are deleted. This allows for relevant data stored in the SRAM to be used for the next command, but then deleted for the next command to be processed. The increase in performance is allowed, while not using extra SRAM or DRAM.

Abstract: A storage device provides thin provisioning by presenting more logical capacity than available physical capacity. The storage device uses a dynamic random-access memory (DRAM) having a size that is proportional to the available physical capacity of the storage device. The storage device includes a memory device with a physical capacity and the DRAM. A controller on the storage device creates segments including logical block address (LBA) sets in an LBA space. The LBA sets include an LBA from each segment that are linked to enable the LBAs in a LBA set to share a mapping space in the DRAM. The controller also creates an L2P table including a LBA set entry per LBA set, with each LBA set entry including sub-entries to store physical locations on the memory device that are associated with the LBAs in the LBA set. The controller also stores the L2P table in the DRAM.

Abstract: The present disclosure generally relates to creating and recalibrating zone groups. Rather than having a fixed zone group size, the zone group size can be dynamic where the data storage device provides a range of zone group sizes to a host device. Based upon block availability and host device commands, new zone groups may be formed of different sizes within the provided range. If there is an insufficient number of blocks available to create a zone group with a size within the provided range, the data storage device can recalibrate. The insufficient number of blocks may be due to bad blocks and/or fragmentation. To obtain more blocks, garbage collection can occur and/or the data storage device can request the host device to release some blocks. The dynamic zone group creation and recalibration ensures more efficient operation of the data storage device.

Abstract: A Controller Memory Buffer (CMB) caching mechanism can be used for increased CMB performance. Rather than reading data and writing data from the static random access memory (SRAM), data is read from the SRAM. When data is read from the CMB in SRAM there is increase performance, but little space to process both read and write commands. Using a dynamic random access memory (DRAM) for write commands and CMB in SRAM for read commands allows for increased performance. Due to limited space in the SRAM, when the read commands are read from the host, the commands are deleted. This allows for relevant data stored in the SRAM to be used for the next command, but then deleted for the next command to be processed. The increase in performance is allowed, while not using extra SRAM or DRAM.

Abstract: The present disclosure generally relates to achieving an acceptable uncorrectable bit error rate (UBER) using a dual temporary data protecting approach and a small SLC cache by adding a temporary XOR protection to zone-groups rather than storing another copy of the zone within the drive. The parity data can be stored with the user data (e.g., as part of the zone-group, effectively increasing zone-group size by 1) or in a separate location, e.g., in an SLC block or another separate MLC block.

Abstract: A Controller Memory Buffer (CMB) caching mechanism can be used for increased CMB performance. Rather than reading data and writing data from the static random access memory (SRAM), data is read from the SRAM. When data is read from the CMB in SRAM there is increase performance, but little space to process both read and write commands. Using a dynamic random access memory (DRAM) for write commands and CMB in SRAM for read commands allows for increased performance. Due to limited space in the SRAM, when the read commands are read from the host, the commands are deleted. This allows for relevant data stored in the SRAM to be used for the next command, but then deleted for the next command to be processed. The increase in performance is allowed, while not using extra SRAM or DRAM.

Abstract: The present disclosure generally relates to creating and recalibrating zone groups. Rather than having a fixed zone group size, the zone group size can be dynamic where the data storage device provides a range of zone group sizes to a host device. Based upon block availability and host device commands, new zone groups may be formed of different sizes within the provided range. If there is an insufficient number of blocks available to create a zone group with a size within the provided range, the data storage device can recalibrate. The insufficient number of blocks may be due to bad blocks and/or fragmentation. To obtain more blocks, garbage collection can occur and/or the data storage device can request the host device to release some blocks. The dynamic zone group creation and recalibration ensures more efficient operation of the data storage device.

Abstract: The present disclosure generally relates to achieving an acceptable uncorrectable bit error rate (UBER) using a dual temporary data protecting approach and a small SLC cache by adding a temporary XOR protection to zone-groups rather than storing another copy of the zone within the drive. The parity data can be stored with the user data (e.g., as part of the zone-group, effectively increasing zone-group size by 1) or in a separate location, e.g., in an SLC block or another separate MLC block.

Abstract: A storage system with a controller having a persistent memory interface to local memory is provided. The persistent memory can be used to store a logical-to-physical address table. A logical-to-physical address table manager, local to the controller or remote in a secondary controller, can be used to access the logical-to-physical address table. The manager can be configured to improve bandwidth and performance in the storage system.

Abstract: A storage system caches logical-to-physical address table entries read in volatile memory. The logical-to-physical address table entries are stored in codewords. The storage system can vary a number or size of an entry in a codeword. Additionally or alternatively, each codeword can store both complete and partial logical-to-physical address table entries. In one example, a codeword having 62 bytes of data and two bytes of error correction code stores 15 complete logical-to-physical address table entries and one partial logical-to-physical address table entry, where the remainder of the partial entry is stored in another codeword. This configuration strikes a good balance between storage space efficiency and random-access write performance.

Abstract: Memories using end-to-end data protection using physical location checks are described. In one aspect, a storage device includes non-volatile memory and a controller coupled to the memory. The controller may receive a write instruction including a data word and a logical address, include metadata with the word including error correction data, identify a physical address in a mapping table based on the logical address, generate a tag corresponding to the physical address, and replace the error correction data with the generated tag or a value based thereon before writing the data word to memory. In one embodiment, the controller may generate the tag concurrently with performing a logical error check using the error correction data.

Abstract: A storage system with a controller having a persistent memory interface to local memory is provided. The persistent memory can be used to store a logical-to-physical address table. A logical-to-physical address table manager, local to the controller or remote in a secondary controller, can be used to access the logical-to-physical address table. The manager can be configured to improve bandwidth and performance in the storage system.

Abstract: A storage system with a controller having a persistent memory interface to local memory is provided. The persistent memory can be used to store a logical-to-physical address table. A logical-to-physical address table manager, local to the controller or remote in a secondary controller, can be used to access the logical-to-physical address table. The manager can be configured to improve bandwidth and performance in the storage system.

Abstract: The present disclosure generally relates to data storage devices comprising one or more memory packages. At least one memory package of the storage device comprises a first stack of memory dies coupled together by a first chip select line and a second stack of memory dies coupled together by a second chip select line. Both the first stack and the second stack comprise a plurality of non-volatile memory dies and a dissimilar memory die disposed on top of the plurality of non-volatile memory dies. Within both the first stack and the second stack, the plurality of non-volatile memory dies is a different type of memory than the dissimilar memory die. Additionally, within both the first stack and the second stack, the plurality of non-volatile memory dies is configured to store host data, and the dissimilar memory die is configured to store cached data.

Abstract: Example storage systems, storage devices, and methods provide secure transfer of data between peer storage devices using protection information. Data operation commands may be received that use a protection information data block format for transferring a target data block between peer storage devices. A local data operation may operate on the target data block in a first storage device and compare at least one protection information tag value to a first data check value. At least one destination verification protection information tag value and the target data block may be transferred to a second storage device through a peer communication channel. The destination verification protection information tag value may be compared to a destination data block protection information tag value by the second storage device. The second storage device may then execute a data operation on the target data block.

Abstract: The present disclosure generally relates to data storage devices comprising one or more memory packages. At least one memory package of the storage device comprises a first stack of memory dies coupled together by a first chip select line and a second stack of memory dies coupled together by a second chip select line. Both the first stack and the second stack comprise a plurality of non-volatile memory dies and a dissimilar memory die disposed on top of the plurality of non-volatile memory dies. Within both the first stack and the second stack, the plurality of non-volatile memory dies is a different type of memory than the dissimilar memory die. Additionally, within both the first stack and the second stack, the plurality of non-volatile memory dies is configured to store host data, and the dissimilar memory die is configured to store cached data.

Abstract: A storage system with a controller having a persistent memory interface to local memory is provided. The persistent memory can be used to store a logical-to-physical address table. A logical-to-physical address table manager, local to the controller or remote in a secondary controller, can be used to access the logical-to-physical address table. The manager can be configured to improve bandwidth and performance in the storage system.

Abstract: Example storage systems, storage devices, and methods provide secure transfer of data between peer storage devices using protection information. Data operation commands may be received that use a protection information data block format for transferring a target data block between peer storage devices. A local data operation may operate on the target data block in a first storage device and compare at least one protection information tag value to a first data check value. At least one destination verification protection information tag value and the target data block may be transferred to a second storage device through a peer communication channel. The destination verification protection information tag value may be compared to a destination data block protection information tag value by the second storage device. The second storage device may then execute a data operation on the target data block.

Abstract: A storage system with a controller having a persistent memory interface to local memory is provided. The persistent memory can be used to store a logical-to-physical address table. A logical-to-physical address table manager, local to the controller or remote in a secondary controller, can be used to access the logical-to-physical address table. The manager can be configured to improve bandwidth and performance in the storage system.