Patents by Inventor Stephen Gualandri

Stephen Gualandri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7864607
    Abstract: Charge pump and discharge circuitry for a non-volatile memory device that splits up the discharge operation into two discharge periods. In a first discharge period, the voltage being discharged (e.g., erase voltage) is discharged through a pair of discharge transistors until the discharging voltage reaches a first voltage level. The path through the pair of discharge transistors is controlled by an intermediate control voltage so that none of the transistors of the pair enter the snapback condition. In the second discharge period, the remaining discharging voltage is fully discharged from the first level through a third discharge transistor.
    Type: Grant
    Filed: July 11, 2007
    Date of Patent: January 4, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Vipul Patel, Stephen Gualandri
  • Publication number: 20070258302
    Abstract: Charge pump and discharge circuitry for a non-volatile memory device that splits up the discharge operation into two discharge periods. In a first discharge period, the voltage being discharged (e.g., erase voltage) is discharged through a pair of discharge transistors until the discharging voltage reaches a first voltage level. The path through the pair of discharge transistors is controlled by an intermediate control voltage so that none of the transistors of the pair enter the snapback condition. In the second discharge period, the remaining discharging voltage is fully discharged from the first level through a third discharge transistor.
    Type: Application
    Filed: July 11, 2007
    Publication date: November 8, 2007
    Inventors: Vipul Patel, Stephen Gualandri
  • Patent number: 7248521
    Abstract: Charge pump and discharge circuitry for a non-volatile memory device that splits up the discharge operation into two discharge periods. In a first discharge period, the voltage being discharged (e.g., erase voltage) is discharged through a pair of discharge transistors until the discharging voltage reaches a first voltage level. The path through the pair of discharge transistors is controlled by an intermediate control voltage so that none of the transistors of the pair enter the snapback condition. In the second discharge period, the remaining discharging voltage is fully discharged from the first level through a third discharge transistor.
    Type: Grant
    Filed: July 12, 2005
    Date of Patent: July 24, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Vipul Patel, Stephen Gualandri
  • Publication number: 20070109877
    Abstract: The present invention provides a method and apparatus for regulating voltages in semiconductor devices. The method and apparatus includes providing a first voltage level using a voltage regulator, determining that a second voltage level is desired and initializing the voltage regulator to provide the second voltage level based on determining that the second voltage level is desired.
    Type: Application
    Filed: January 3, 2007
    Publication date: May 17, 2007
    Inventors: Theodore Pekny, Stephen Gualandri
  • Publication number: 20070014170
    Abstract: Charge pump and discharge circuitry for a non-volatile memory device that splits up the discharge operation into two discharge periods. In a first discharge period, the voltage being discharged (e.g., erase voltage) is discharged through a pair of discharge transistors until the discharging voltage reaches a first voltage level. The path through the pair of discharge transistors is controlled by an intermediate control voltage so that none of the transistors of the pair enter the snapback condition. In the second discharge period, the remaining discharging voltage is fully discharged from the first level through a third discharge transistor.
    Type: Application
    Filed: July 12, 2005
    Publication date: January 18, 2007
    Inventors: Vipul Patel, Stephen Gualandri
  • Publication number: 20050201161
    Abstract: An erase discharge circuit in a flash memory is coupled to an array source and a p-well drive and receives first and second discharge signals. The erase discharge circuit operates during a discharge cycle in a first mode in response to the first discharge signal to couple the first node to the second node and to discharge voltages on the first and second nodes at a first rate. The erase discharge circuit operates in a second mode in response to the second discharge signal to couple the first node to the second node to discharge the voltages on the first and second nodes at a second rate.
    Type: Application
    Filed: March 14, 2005
    Publication date: September 15, 2005
    Inventors: Stephen Gualandri, Theodore Pekny
  • Publication number: 20050081013
    Abstract: A multiple partition memory and architecture for concurrent operations reduces circuit overhead by providing a common read sense amplifier and program path for multiple partitions. Long separate datalines for read and algorithm operations allow concurrent operation and blockout of multiple operations in a single block of the memory.
    Type: Application
    Filed: October 10, 2003
    Publication date: April 14, 2005
    Inventors: Theodore Pekny, Stephen Gualandri
  • Publication number: 20050013189
    Abstract: The present invention provides a method and apparatus for regulating voltages in semiconductor devices. The method and apparatus includes providing a first voltage level using a voltage regulator, determining that a second voltage level is desired and initializing the voltage regulator to provide the second voltage level based on determining that the second voltage level is desired.
    Type: Application
    Filed: August 13, 2004
    Publication date: January 20, 2005
    Inventors: Theodore Pekny, Stephen Gualandri