Abstract: Mobile management method, system and client. Method includes receiving a DNS query for a host name from an application on client; retrieving reputation data associated with host name from a local cache on client; and determining a policy based on host name and the reputation data. Based on determined policy for the host name, blocking attempted network flows to a host corresponding to host name to produce blocked attempted network flows. Method also includes sending attempted network flow metadata related to the blocked attempted network flows to a collector on client; transmitting the attempted network flow metadata from the collector to a VPN server pool via a VPN tunnel; and producing an anomaly report from the transmitted attempted network flow metadata. The anomaly report includes at least one of anomalies, cohorts, trends, location boundaries, detected network security issues, detected compromised clients and/or optimized network usage.

Abstract: A thermal management scheme, for a multichip module, that is aware of various dies in a stack (horizontal and/or vertical) and heat generated from them, local hot spots in a victim die, and hot spots in aggressor die(s). Each victim die receives telemetry information from thermal sensors located in aggressor dies as well as local thermal sensors in the victim die. The telemetry information is used to enable a virtual sensing scheme where temperature for a target die (e.g., a victim die) and/or its intellectual property (IP) domain is estimated or calculated. The estimated or calculated temperature is then used for performance management of the victim and/or aggressor dies in the stack.

Abstract: A power supply architecture combines the benefits of a traditional single stage power delivery, when there are no additional power losses in the integrated VR with low VID and low CPU losses of FIVR (fully integrated voltage regulator) and D-LVR (digital linear voltage regulator). The D-LVR is not in series with the main power flow, but in parallel. By placing the digital-LVR in parallel to a primary VR (e.g., motherboard VR), the CPU VID is lowered and the processor core power consumption is lowered. The power supply architecture reduces the guard band for input power supply level, thereby reducing the overall power consumption because the motherboard VR specifications can be relaxed, saving cost and power. The power supply architecture drastically increases the CPU performance at a small extra cost for the silicon and low complexity of tuning.

Abstract: An apparatus is provided, where the apparatus includes a plurality of processing cores to execute a plurality of processes, a register to store an indicator that is to indicate a preference for either performance or energy efficiency, a first circuitry to determine an effective utilization of a first processing core, based on the indicator, and a second circuitry to select at least one of an operating voltage or an operating frequency of the first processing core, based at least in part on the effective utilization of the first processing core.

Abstract: A power supply architecture combines the benefits of a traditional single stage power delivery, when there are no additional power losses in the integrated VR with low VID and low CPU losses of FIVR (fully integrated voltage regulator) and D-LVR (digital linear voltage regulator). The D-LVR is not in series with the main power flow, but in parallel. By placing the digital-LVR in parallel to a primary VR (e.g., motherboard VR), the CPU VID is lowered and the processor core power consumption is lowered. The power supply architecture reduces the guard band for input power supply level, thereby reducing the overall power consumption because the motherboard VR specifications can be relaxed, saving cost and power. The power supply architecture drastically increases the CPU performance at a small extra cost for the silicon and low complexity of tuning.

Abstract: A scheme for measuring AC and DC load-line (LL) using voltage and current monitoring apparatus. During calibration for LL measurement, a tested or known workload is executed on a processor or system-on-chip (SoC). The calibration can be done when the processor is first used in a real-time system (customer) scenario, or repeated whenever necessary to compensate silicon aging or other effects that affect the LL values. LL is estimated, determined, and/or calculated for each power supply rail in the processor or SoC. The measured LL is used in calculations that determine the operating voltage of an input voltage regulator (VR) at run time, thereby optimizing the power/performance characteristics of that specific system.

Abstract: An apparatus is provided, where the apparatus includes a plurality of processing cores to execute a plurality of processes, a register to store an indicator that is to indicate a preference for either performance or energy efficiency, a first circuitry to determine an effective utilization of a first processing core, based on the indicator, and a second circuitry to select at least one of an operating voltage or an operating frequency of the first processing core, based at least in part on the effective utilization of the first processing core.

Abstract: An apparatus for permitting a decoy system to be activated by a jerk cord with little motion and force. An apparatus comprising of a pulley, a swivel, and a shackling mechanism used to attach to an anchoring system. The system is self righting when deployed and relatively easy to activate compared to other systems available.

Abstract: According to one embodiment of the invention, an integrated circuit device at least one compute engine and a control unit. Coupled to the compute engine(s), the control unit is adapted to dynamically control an energy-efficient operating setting of at least one power management parameter for the integrated circuit device after execution of Basic Input/Output System (BIOS) has already completed.

Abstract: An apparatus for holding ammunition comprising a support backing, at least one retaining device to hold one end of the ammunition, and at least one magnet attached to the support backing. The retaining device may receive the first end of the ammunition and the magnet magnetically attaches to a second end of the ammunition, such that that the ammunition is held in place.

Abstract: A bone fixation device is provided with an elongate body having a longitudinal axis and having a first state in which at least a portion of the body is flexible and a second state in which the body is generally rigid, an actuateable gripper disposed at one or more locations on the elongated body, a hub located on a proximal end of the elongated body, and an actuator operably connected to the gripper(s) to deploy the gripper(s) from a retracted configuration to an expanded configuration. Methods of repairing a fracture of a bone are also disclosed. One such method comprises inserting a bone fixation device into an intramedullary space of the bone to place at least a portion of an elongate body of the fixation device in a flexible state on one side of the fracture and at least a portion of a hub on another side of the fracture, and operating an actuator to deploy at least one gripper of the fixation device to engage an inner surface of the intramedullary space to anchor the fixation device to the bone.

Abstract: In an embodiment, a processor includes at least one processor core and power control logic having energy usage logic to predict an energy usage of the processor and a voltage regulator coupled to the processor, during a low power period according to a first voltage regulator control mode and a second voltage regulator control mode, and to control the voltage regulator based at least in part on the predicted energy usage. Other embodiments are described and claimed.

Abstract: According to one embodiment of the invention, an integrated circuit device at least one compute engine and a control unit. Coupled to the compute engine(s), the control unit is adapted to dynamically control an energy-efficient operating setting of at least one power management parameter for the integrated circuit device after execution of Basic Input/Output System (BIOS) has already completed.

Abstract: In one embodiment, the present invention includes a processor having a core with decode logic to decode an instruction prescribing an identification of a location to be monitored and a timer value, and a timer coupled to the decode logic to perform a count with respect to the timer value. The processor may further include a power management unit coupled to the core to determine a type of a low power state based at least in part on the timer value and cause the processor to enter the low power state responsive to the determination. Other embodiments are described and claimed.

Abstract: A frosting system is disclosed. The frosting system includes a base material in a container and at least one packet. The packet may contain one or more flavor additives and/or one or more color additives. A user adds one or more packets to a base material in a container and mixes the packet(s) with the base material to arrive at a final frosting. Related methods and display units are also disclosed.

Abstract: Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.

Abstract: A bone fixation device is provided with an elongate body having a longitudinal axis and having a first state in which at least a portion of the body is flexible and a second state in which the body is generally rigid, an actuateable gripper disposed at one or more locations on the elongated body, a hub located on a proximal end of the elongated body, and an actuator operably connected to the gripper(s) to deploy the gripper(s) from a retracted configuration to an expanded configuration. Methods of repairing a fracture of a bone are also disclosed. One such method comprises inserting a bone fixation device into an intramedullary space of the bone to place at least a portion of an elongate body of the fixation device in a flexible state on one side of the fracture and at least a portion of a hub on another side of the fracture, and operating an actuator to deploy at least one gripper of the fixation device to engage an inner surface of the intramedullary space to anchor the fixation device to the bone.

Abstract: For one disclosed embodiment, modulation circuitry may control power conversion circuitry to supply power for one or more load circuits. Voltage regulation control circuitry may control the modulation circuitry to regulate voltage supply from the power conversion circuitry. Current surge balance control circuitry may separately control the modulation circuitry to provide supply current steps by the power conversion circuitry to help cancel load current surges. Other embodiments are also disclosed.

Abstract: Methods and circuits to define a thermal operating mode for a integrated device by defining an operating voltage and a frequency range.

Abstract: The invention features a glenoid (shoulder socket) implant prosthesis, a humeral implant prosthesis, devices for implanting glenoid and humeral implant prostheses, and methods of their use for the treatment an injured or damaged shoulder.