Patents by Inventor Stephen H. Hall
Stephen H. Hall has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210392743Abstract: Apparatus and methods employing twisted differential compensation for routing high-speed signals near power delivery inductors. Traces used for a high-speed differential signal including a P trace and an N trace are routed through one or more layers in a multi-layer printed circuit board (PCB) substrate and employ a twisted portion proximate to the centerline of an inductor under which portions of the P and N traces are swapped horizontally in a layer parallel to the top plane and/or are swapped vertically by swapping layers. The signal paths are routed such that a level of noise inductively coupled into the P trace and the N trace from the inductor is approximately equally. Stripline structures may be used for signals that are routed under an inductor, while stripline and microstrip structures may be used for signals routed adjacent to an inductor.Type: ApplicationFiled: August 30, 2021Publication date: December 16, 2021Inventors: Long WANG, Ranjul BALAKRISHNAN, Stephen H. HALL
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Patent number: 11178768Abstract: Three-dimensional (3-D) volumetric board architectural design provides technical solutions to technical problems facing miniaturization of circuit boards. The 3-D volumetric architecture includes using more of the unused volume in the vertical dimension (e.g., Z-dimension) to increase the utilization of the total circuit board volume. The 3-D volumetric architecture is realized by mounting components on a first PCB and on a second PCB, and inverting and suspending the second PCB above the first PCB. The use of 3-D volumetric board architectural design further enables formation of a shielded FEMIE, providing shielding and improved volumetric use with little or no reduction in system performance or increase in system Z-height.Type: GrantFiled: April 1, 2016Date of Patent: November 16, 2021Assignee: Intel CorporationInventors: Khang Choong Yong, Stephen H. Hall, Tin Poay Chuah, Boon Ping Koh, Eng Huat Goh
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Patent number: 10877559Abstract: This disclosure is directed to a system to provide tactile feedback during non-contact interaction. A system may comprise at least display circuitry, sensing circuitry, tactile feedback circuitry and processing circuitry. The processing circuitry may cause the display circuitry to present a user interface. The sensing circuitry may sense when a body part of a user (e.g., a hand, a finger, etc.) is proximate to the user interface and may generate position data based on a sensed position of the body part. The processing circuitry may determine a relative position of the body part with respect to the user interface based on the position data, and may determine if the body part is interacting with the user interface based on the relative position. If it is determined that the body part is interacting with the user interface, the processing circuitry may cause the tactile feedback circuitry to generate directional feedback.Type: GrantFiled: March 29, 2016Date of Patent: December 29, 2020Assignee: Intel CorporationInventors: Kevin J. Doran, Stephen H. Hall, Murali Veeramoney, Vijay M. Rao, Royce Fernald
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Patent number: 10652999Abstract: Embodiments are generally directed to a mutual inductance suppressor for crosstalk immunity enhancement. An embodiment of a printed circuit board includes a first signal trace and a second signal trace on a first layer, wherein the first signal trace and second signal trace are non-intersecting; a second layer below the first layer, the second layer including a voltage reference plane; and a mutual inductance suppressor in the voltage reference plane, the mutual inductance suppressor including a serpentine portion of the voltage reference plane between the first signal trace and the second signal trace.Type: GrantFiled: October 1, 2016Date of Patent: May 12, 2020Assignee: Intel CorporationInventors: Khang Choong Yong, Jackson Chung Peng Kong, Bok Eng Cheah, Stephen H. Hall
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Publication number: 20190215953Abstract: Embodiments are generally directed to a mutual inductance suppressor for crosstalk immunity enhancement. An embodiment of a printed circuit board includes a first signal trace and a second signal trace on a first layer, wherein the first signal trace and second signal trace are non-intersecting; a second layer below the first layer, the second layer including a voltage reference plane; and a mutual inductance suppressor in the voltage reference plane, the mutual inductance suppressor including a serpentine portion of the voltage reference plane between the first signal trace and the second signal trace.Type: ApplicationFiled: October 1, 2016Publication date: July 11, 2019Inventors: Khang Choong YONG, Jackson Chung Peng KONG, Bok Eng CHEAH, Stephen H. HALL
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Patent number: 10078612Abstract: An apparatus is described herein. The apparatus includes a plurality of conductors, wherein at least one conductor is a common-mode conductor. The apparatus also includes an encoder to encode data to be transmitted on the plurality of conductors, wherein a data speed of the common-mode conductor is limited and a data speed of other conductors is maximized according to an encoding matrix.Type: GrantFiled: July 28, 2014Date of Patent: September 18, 2018Assignee: Intel CorporationInventors: Michael W. Leddige, Stephen H. Hall, Chaitanya Sreerama, Olufemi B. Oluwafemi, Antonio Zenteno Ramirez, Maynard C. Falconer
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Patent number: 10073807Abstract: A logic-based decoder recovers binary data from ternary Crosstalk-Harnessed Signaling (CHS) streams with lower part cost, complexity and power consumption than analog/digital converter (ADC)-based CHS decoders. The decoders use inverters, latches, gates, latching circuits, and one comparator per bit pair to carry out the decoding calculations to produce a reconstructed binary signal with very low crosstalk noise that is largely insensitive to routing density. System-on-chip, multi-chip package, printed circuit board, and wired network applications are discussed.Type: GrantFiled: December 1, 2015Date of Patent: September 11, 2018Assignee: Intel CorporationInventors: Chaitanya Sreerama, Stephen H. Hall
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Publication number: 20170285745Abstract: This disclosure is directed to a system to provide tactile feedback during non-contact interaction. A system may comprise at least display circuitry, sensing circuitry, tactile feedback circuitry and processing circuitry. The processing circuitry may cause the display circuitry to present a user interface. The sensing circuitry may sense when a body part of a user (e.g., a hand, a finger, etc.) is proximate to the user interface and may generate position data based on a sensed position of the body part. The processing circuitry may determine a relative position of the body part with respect to the user interface based on the position data, and may determine if the body part is interacting with the user interface based on the relative position. If it is determined that the body part is interacting with the user interface, the processing circuitry may cause the tactile feedback circuitry to generate directional feedback.Type: ApplicationFiled: March 29, 2016Publication date: October 5, 2017Applicant: Intel CorporationInventors: KEVIN J. DORAN, STEPHEN H. HALL, MURALI VEERAMONEY, VIJAY M. RAO, ROYCE FERNALD
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Publication number: 20170290154Abstract: Three-dimensional (3-D) volumetric board architectural design provides technical solutions to technical problems facing miniaturization of circuit boards. The 3-D volumetric architecture includes using more of the unused volume in the vertical dimension (e.g., Z-dimension) to increase the utilization of the total circuit board volume. The 3-D volumetric architecture is realized by mounting components on a first PCB and on a second PCB, and inverting and suspending the second PCB above the first PCB. The use of 3-D volumetric board architectural design further enables formation of a shielded FEMIE, providing shielding and improved volumetric use with little or no reduction in system performance or increase in system Z-height.Type: ApplicationFiled: April 1, 2016Publication date: October 5, 2017Inventors: Khang Choong Yong, Stephen H. Hall, Tin Poay Chuah, Boon Ping Koh, Eng Huat Goh
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Publication number: 20170154007Abstract: A logic-based decoder recovers binary data from ternary Crosstalk-Harnessed Signaling (CHS) streams with lower part cost, complexity and power consumption than analog/digital converter (ADC)-based CHS decoders. The decoders use inverters, latches, gates, latching circuits, and one comparator per bit pair to carry out the decoding calculations to produce a reconstructed binary signal with very low crosstalk noise that is largely insensitive to routing density. System-on-chip, multi-chip package, printed circuit board, and wired network applications are discussed.Type: ApplicationFiled: December 1, 2015Publication date: June 1, 2017Inventors: Chaitanya Sreerama, Stephen H. Hall
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Patent number: 9632961Abstract: Techniques for decoding encoded data are described herein. An example of a device in accordance with the present techniques includes a receiving signaling module coupled to a plurality of signal lines. The signaling module includes a receiver to receive a plurality of encoded line voltages or currents on the plurality of signal lines of a bus, wherein each one of the plurality of encoded line voltages corresponds to a weighted sum of data. The signaling module includes a comparator to determine the voltage level of each line at a unit interval and convert the voltage level to a digital value. The signaling module includes a lookup table correlating the digital value with a digital bit stream.Type: GrantFiled: March 15, 2013Date of Patent: April 25, 2017Assignee: INTEL CORPORATIONInventors: Olufemi B. Oluwafemi, Stephen H. Hall, Jason A. Mix, Earl J. Wight, Chaitanya Sreerama, Michael W. Leddige, Paul G. Huray
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Patent number: 9618393Abstract: The present invention comprises an optical train (50) and optional wavelength-selective photodetectors. The optical train (50) uses reflecting elements (600) including mirrors and/or prisms to fold the light path of the transmitted UV light beam to direct it through the body (100) of the instrument, through a sample vessel (200) using at least one pass but preferably two or more passes and into illumination contact with a photodetector (400). With each additional pass, the Beer-Lambert path length is effectively increased. Separate second optical train (53) and third optical train (54) exist for the detection and measurement of scattered light by illumination contact with one or more photodetectors.Type: GrantFiled: September 24, 2014Date of Patent: April 11, 2017Assignee: Freestone Environmental Services, Inc.Inventors: Stephen H Hall, Kimberly Anne Schuyler
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Patent number: 9552995Abstract: Some example forms relate to an electrical interconnect for an electronic package. The electrical interconnect includes a dielectric layer that includes a trench formed into one surface of the dielectric layer and a signal conductor that fills the trench and extends above the one surface of dielectric layer. The electrical interconnect further includes a conductive reference layer mounted on an opposing side of the dielectric layer. The conductive reference layer is electromagnetically coupled to the signal conductor when current passes through the signal conductor.Type: GrantFiled: November 26, 2014Date of Patent: January 24, 2017Assignee: Intel CorporationInventors: Khang Choong Yong, Bok Eng Cheah, Teong Keat Beh, Howard L. Heck, Jackson Chung Peng Kong, Stephen H. Hall, Kooi Chi Ooi
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Publication number: 20160380326Abstract: Techniques and mechanisms for enabling small radius bending of a flexible circuit. In an embodiment, the flexible circuit includes a first section, a second section and a third section between the first section and second section. Stacked structures of the first section include a first trace portion and a first conductor, and stacked structures of the second section include a second trace portion and a second conductor. In another embodiment, a first span structure of the third section exchanges a first signal between the first trace portion and the second trace portion while the first conductor and the second conductor are maintained at a reference potential. While the first signal is exchanged, a second span structure of the third section—coplanar with the first span structure—is maintained at the reference potential or propagates a second signal complementary to the first signal.Type: ApplicationFiled: June 26, 2015Publication date: December 29, 2016Inventors: Stephen H. Hall, Vijay Kasturi, Michael T. Hamann
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Patent number: 9515402Abstract: Techniques and mechanisms for coupling a flexible circuit device to another device. In an embodiment, a substrate includes a first side and a second side opposite the first side, where first contacts of a hardware interface are disposed on the first side, and second contacts of the hardware interface are disposed on the second side. First interconnects and second interconnects variously extend in the substrate, where the first contacts are coupled via the first side each to a respective one of the first interconnects, and the second contacts are coupled via the second side each to a respective one of the second interconnects. In another embodiment, the substrate is one of a flexible substrate and a printed circuit board substrate, where the first interface is configured to couple the substrate, in an edge-to-edge configuration, with the other of a flexible substrate and a printed circuit board substrate.Type: GrantFiled: September 25, 2015Date of Patent: December 6, 2016Assignee: Intel CorporationInventors: Xiang Li, Stephen H. Hall
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Publication number: 20160174362Abstract: Techniques and mechanisms to mitigate noise in a signal line extending across rails arranged in a split plane configuration. In an embodiment, respective sides of a first rail and a second rail define opposite sides of a boundary region between the rails. The first rail forms a groove and the second rail forms a branch portion that extends at least in part into the groove. In another embodiment, one or more signal lines each extend across the boundary region and proximate to the branch portion, the one or more signals each to communicate a respective signal while the first rail is at a first voltage and while the second rail is at a second voltage. The branch portion and groove contribute to a reduced impedance discontinuity across the boundary region, which mitigates the creation of signal noise in the one or more signal lines.Type: ApplicationFiled: December 12, 2014Publication date: June 16, 2016Inventors: Kevin J. Doran, Stephen H. Hall, Thomas D. Whiteley, Kai Xiao, Yuan-Liang Li, Jimmy Hsu, Thonas Yi-Ren Su
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Publication number: 20160148866Abstract: Some example forms relate to an electrical interconnect for an electronic package. The electrical interconnect includes a dielectric layer that includes a trench formed into one surface of the dielectric layer and a signal conductor that fills the trench and extends above the one surface of dielectric layer. The electrical interconnect further includes a conductive reference layer mounted on an opposing side of the dielectric layer. The conductive reference layer is electromagnetically coupled to the signal conductor when current passes through the signal conductor.Type: ApplicationFiled: November 26, 2014Publication date: May 26, 2016Inventors: Khang Choong Yong, Bok Eng Cheah, Teong Keat Beh, Howard L. Heck, Jackson Chung Peng Kong, Stephen H. Hall, Kooi Chi Ooi
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Patent number: 9330039Abstract: Techniques for encoding data are described herein. An example of a device in accordance with the present techniques includes a signaling module coupled to a plurality of digital inputs. The signaling module is to encode data received at the plurality of digital inputs to generate encoded data. Based on the encoded data, the signaling module can drive line voltages on a plurality of signal lines of a bus. Each one of the plurality of line voltages corresponds to a weighted sum of the data received at the plurality of digital inputs.Type: GrantFiled: December 26, 2012Date of Patent: May 3, 2016Assignee: Intel CorporationInventors: Stephen H. Hall, Chaitanya Sreerama, Jason A. Mix, Michael W. Leddige, Jose A. Sanchez Sanchez, Olufemi B. Oluwafemi, Paul G. Huray, Maynard C. Falconer
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Publication number: 20160084759Abstract: The present invention comprises an optical train (50) and optional wavelength-selective photodetectors. The optical train (50) uses reflecting elements (600) including mirrors and/or prisms to fold the light path of the transmitted UV light beam to direct it through the body (100) of the instrument, through a sample vessel (200) using at least one pass but preferably two or more passes and into illumination contact with a photodetector (400). With each additional pass, the Beer-Lambert path length is effectively increased. Separate second optical train (53) and third optical train (54) exist for the detection and measurement of scattered light by illumination contact with one or more photodetectors.Type: ApplicationFiled: September 24, 2014Publication date: March 24, 2016Inventors: Stephen H Hall, Kimberly Anne Schuyler
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Publication number: 20160026597Abstract: An apparatus is described herein. The apparatus includes a plurality of conductors, wherein at least one conductor is a common-mode conductor. The apparatus also includes an encoder to encode data to be transmitted on the plurality of conductors, wherein a data speed of the common-mode conductor is limited and a data speed of other conductors is maximized according to an encoding matrix.Type: ApplicationFiled: July 28, 2014Publication date: January 28, 2016Inventors: Michael W. Leddige, Stephen H. Hall, Chaitanya Sreerama, Olufemi B. Oluwafemi, Antonio Zenteno Ramirez, Maynard C. Falconer