Abstract: A PWM signal of substantially constant amplitude is supplied to a B+ compensation circuit, for developing a vertical ramp voltage in a digital TV. One transistor of a current switching differentially coupled pair is supplied with the PWM signal and the other is properly biased so as to amplify the PWM signal without inverting its phase. The negative peaks of the PWM signal are clamped to voltage which varies with B+ and the positive peak of the PWM signal are a fraction of B+. However, the positive peaks vary more with B+ than do the negative peaks. The amplitude of the PWM signal, which is used for developing the vertical ramp, is the difference of the positive peak and the negative peak and therefore it will vary with B+. The B+ in the television receiver varies with beam current and by properly varying the vertical ramp in accordance with the variation in B+, the vertical size of the raster can be maintained.

Abstract: This invention permits horizontal centering of a television picture on the screen. Signals normally present within a television receiver are used to generate intermediate signals for centering the picture. The method of operation provides satisfactory noise immunity while maintaining adequate display characteristics. A two loop system is used. The first loop receives the horizontal sync and generates an intermediate signal in response. The second loop variably delays the intermediate signal to create a signal which is phase locked to the flyback signal. In this fashion, the flyback signal may be made to be symmetric with the horizontal blanking interval rather than the horizontal sync pulse, thus centering the video information on the screen.

Abstract: A biased current mirror comprises first and second transistor having their emitters connected to ground and their bases connected together. The collectors of the transistors are connected to connector pads on an integrated circuit. Bias current is supplied to the input of the current mirror to keep the base-emitter capacitances of the transistors charged despite a cutoff of input current. An offset current, proportional to the bias current is supplied to the output of the current mirror to offset the output current response of the mirror to the bias current. A current-capacitance oscillator including two biased current mirrors comprises differentially coupled pairs of transistors with the biased current mirrors controlling the charge and discharge of a timing capacitor. A conventional phase detector circuit incorporates a biased current mirror to minimize switching error due to delays associated with junction capacitors of the transistors.

Abstract: A system for generating 2H pulses by counting cycles of reference signals whose frequency is related to the frequency of a color subcarrier signal. In one embodiment, four such reference signals are provided, each phase separated from the other by ninety degrees. A counter receives one of the reference signals for counting its cycles up to a preselected integral count. When the preselected count is reached, further circuitry generates an output pulse for clearing the counter and holding it cleared while the next reference signal is applied to the counter. The cycle of counting reference signal cycles, clearing the counter, and applying the next reference signal to the counter continues such that the four reference signals are applied to the counter sequentially. By proper selection of the integral count reached by the counter and the duration of its cleared state, the output pulses are developed at a 2H rate.