Patents by Inventor Stephen H. Perlmutter

Stephen H. Perlmutter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11829270
    Abstract: Apparatus and method for a die kill and recovery sequence for a non-volatile memory (NVM). Data are stored in the NVM as data sets in garbage collection units (GCUs) that span multiple semiconductor dies. A die failure management circuit is configured to detect a die failure event associated with a selected die, and to generate a recovery strategy to accommodate the detected die failure event by selecting recovery actions to be taken in a selected sequence to maintain a current level of data transfer performance with a client device. The selected recovery actions are carried out in the selected sequence to transfer at least a portion of the user data stored in the selected die to a new replacement die, after which the selected die is decommissioned from further use. The NVM may be a flash memory of a solid-state drive (SSD).
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: November 28, 2023
    Assignee: Seagate Technology LLC
    Inventors: Stacey Secatch, Stephen H. Perlmutter, Matthew Stoering, Jonathan Henze
  • Patent number: 11334481
    Abstract: Apparatus and method for managing a non-volatile memory (NVM) such as a flash memory in a solid-state drive (SSD). In some embodiments, the NVM is arranged as a plurality of semiconductor memory dies coupled to a controller circuit using a plurality of channels. The controller circuit divides the plurality of dies into a succession of garbage collection units (GCUs). Each GCU is independently erasable and allocatable for storage of user data. The GCUs are staggered so that each GCU is formed from a different subset of the dies in the NVM. In further embodiments, the dies are arranged into NVM sets in accordance with the NVMe (Non-Volatile Memory Express) specification with each NVM set addressable by a different user for storage of data in a separate set of staggered GCUs.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: May 17, 2022
    Inventors: Stephen H. Perlmutter, Stacey Secatch, Andrew Louder
  • Publication number: 20220138065
    Abstract: Apparatus and method for a die kill and recovery sequence for a non-volatile memory (NVM). Data are stored in the NVM as data sets in garbage collection units (GCUs) that span multiple semiconductor dies. A die failure management circuit is configured to detect a die failure event associated with a selected die, and to generate a recovery strategy to accommodate the detected die failure event by selecting recovery actions to be taken in a selected sequence to maintain a current level of data transfer performance with a client device. The selected recovery actions are carried out in the selected sequence to transfer at least a portion of the user data stored in the selected die to a new replacement die, after which the selected die is decommissioned from further use. The NVM may be a flash memory of a solid-state drive (SSD).
    Type: Application
    Filed: November 1, 2021
    Publication date: May 5, 2022
    Inventors: Stacey Secatch, Stephen H. Perlmutter
  • Publication number: 20220113898
    Abstract: A data storage system may have a plurality of memory cells located in different data storage devices that are arranged into a plurality of logical namespaces with each logical namespace configured to be sequentially written and entirely erased as a single unit. An asymmetry strategy may be proactively created with the asymmetry module in response to data access activity to the logical namespaces by the asymmetry module. A new mode, as prescribed by the asymmetry strategy, is entered for at least one logical namespace in response to an operational trigger being met. The new mode changes a timing of at least one queued data access request to at least one logical namespace.
    Type: Application
    Filed: October 8, 2021
    Publication date: April 14, 2022
    Inventors: Stacey Secatch, David W. Claude, Daniel J. Benjamin, Thomas V. Spencer, Matthew B. Lovell, Steven Williams, Stephen H. Perlmutter
  • Patent number: 11301376
    Abstract: A data storage device can be arranged with a semiconductor memory having a plurality of erasure blocks accessed by a controller to store data. An access count for each respective erasure block can be generated to allow a wear range for the semiconductor memory to be computed based on the respective access counts with the controller. A performance impact of the wear range is evaluated with the controller in order to intelligently alter a deterministic window of a first erasure block of the plurality of erasure blocks in response to the performance impact.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: April 12, 2022
    Inventors: Stephen H. Perlmutter, Kyumsung Lee
  • Patent number: 11138069
    Abstract: Apparatus and method for storing data in a non-volatile memory (NVM), such as a flash memory in a solid-state drive (SSD). In some embodiments, a distributed storage space of the NVM is defined to extend across a plural number of regions of the NVM. A non-standard parity data set is provided having a plural number of data elements greater than or equal to the plural number of regions in the storage space. The data set is written by storing a first portion of the data elements and a first parity value to the plural number of regions and a remaining portion of the data elements and a second parity value to a subset of the plural number of regions. The regions can comprise semiconductor dies in a flash memory, and the distributed storage space can be a garbage collection unit formed using one erasure block from each flash die.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: October 5, 2021
    Assignee: Seagate Technology, LLC
    Inventors: Stephen H. Perlmutter, Steven S. Williams, Benjamin J. Scott, Andrew J. Louder, Kyumsung Lee, Robert W. Dixon
  • Patent number: 11017098
    Abstract: Apparatus and method for managing entropy in a cryptographic processing system, such as but not limited to a solid-state drive (SSD). In some embodiments, a processing device is operated to transfer data between a host device and a non-volatile memory (NVM). In response to the detection of a power down event associated with the processing device, entropy associated with the power down event is collected and stored in a memory. Upon a subsequent reinitialization of the processing device, the entropy is conditioned and used as an input to a cryptographic function to subsequently transfer data between the host device and the NVM. In some embodiments, the entropy is obtained from the state of a hardware timer that provides a monotonically increasing count for timing control. In other embodiments, the entropy is obtained from a RAID buffer used to store data to a die set of the NVM.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: May 25, 2021
    Assignee: Seagate Technology LLC
    Inventors: Stacey Secatch, Steven S. Williams, David W. Claude, Benjamin J. Scott, Kyumsung Lee, Stephen H. Perlmutter
  • Patent number: 10896002
    Abstract: Apparatus and method for managing metadata in a data storage device such as a solid-state drive (SSD). In some embodiments, a write stream is formed of user data blocks to be sequentially written to a non-volatile memory (NVM). An entry of a reverse directory footer is generated for each user data block in the write stream to describe a physical address in the NVM at which the corresponding user data block is to be stored. The entries are accumulated in a buffer memory until the total count of entries reaches a predetermined threshold and a complete footer data structure is formed. The complete footer data structure is thereafter inserted into the write stream for writing, with the data blocks, to the NVM. The complete footer data structure has an overall size that corresponds to an overall size of each of the user data blocks.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: January 19, 2021
    Assignee: Seagate Technology LLC
    Inventors: Benjamin J. Scott, Steven S. Williams, Stephen H. Perlmutter, Ryan J. Goss, Daniel J. Benjamin
  • Publication number: 20200379903
    Abstract: Apparatus and method for managing a non-volatile memory (NVM) such as a flash memory in a solid-state drive (SSD). In some embodiments, the NVM is arranged as a plurality of semiconductor memory dies coupled to a controller circuit using a plurality of channels. The controller circuit divides the plurality of dies into a succession of garbage collection units (GCUs). Each GCU is independently erasable and allocatable for storage of user data. The GCUs are staggered so that each GCU is formed from a different subset of the dies in the NVM. In further embodiments, the dies are arranged into NVM sets in accordance with the NVMe (Non-Volatile Memory Express) specification with each NVM set addressable by a different user for storage of data in a separate set of staggered GCUs.
    Type: Application
    Filed: August 18, 2020
    Publication date: December 3, 2020
    Inventors: Stephen H. Perlmutter, Stacey Secatch, Andrew Louder
  • Patent number: 10783982
    Abstract: A data storage system can receive a data write request to write data to a physical address of a non-volatile semiconductor memory prior to detecting an error while storing the write data to the physical address. The detected error is corrected with a monitor module connected to the non-volatile semiconductor memory and a counter associated with the physical address is incremented with the monitor module in response to the corrected error. The write data can be subsequently read to a host in response to a data read request.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: September 22, 2020
    Assignee: Seagate Technology LLC
    Inventor: Stephen H. Perlmutter
  • Patent number: 10747662
    Abstract: Apparatus and method for managing a non-volatile memory (NVM) such as a flash memory in a solid-state drive (SSD). In some embodiments, the NVM is arranged as a plurality of semiconductor memory dies coupled to a controller circuit using a plurality of channels. The controller circuit divides the plurality of dies into a succession of garbage collection units (GCUs). Each GCU is independently erasable and allocatable for storage of user data. The GCUs are staggered so that each GCU is formed from a different subset of the dies in the NVM. In further embodiments, the dies are arranged into NVM sets in accordance with the NVMe (Non-Volatile Memory Express) specification with each NVM set addressable by a different user for storage of data in a separate set of staggered GCUs.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: August 18, 2020
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Stephen H. Perlmutter, Stacey Secatch, Andrew Louder
  • Publication number: 20200004676
    Abstract: Apparatus and method for managing a non-volatile memory (NVM) such as a flash memory in a solid-state drive (SSD). In some embodiments, the NVM is arranged as a plurality of semiconductor memory dies coupled to a controller circuit using a plurality of channels. The controller circuit divides the plurality of dies into a succession of garbage collection units (GCUs). Each GCU is independently erasable and allocatable for storage of user data. The GCUs are staggered so that each GCU is formed from a different subset of the dies in the NVM. In further embodiments, the dies are arranged into NVM sets in accordance with the NVMe (Non-Volatile Memory Express) specification with each NVM set addressable by a different user for storage of data in a separate set of staggered GCUs.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventors: Stephen H. Perlmutter, Stacey Secatch, Andrew Louder
  • Publication number: 20200004971
    Abstract: Apparatus and method for managing entropy in a cryptographic processing system, such as but not limited to a solid-state drive (SSD). In some embodiments, a processing device is operated to transfer data between a host device and a non-volatile memory (NVM). In response to the detection of a power down event associated with the processing device, entropy associated with the power down event is collected and stored in a memory. Upon a subsequent reinitialization of the processing device, the entropy is conditioned and used as an input to a cryptographic function to subsequently transfer data between the host device and the NVM. In some embodiments, the entropy is obtained from the state of a hardware timer that provides a monotonically increasing count for timing control. In other embodiments, the entropy is obtained from a RAID buffer used to store data to a die set of the NVM.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 2, 2020
    Inventors: Stacey Secatch, Steven S. Williams, David W. Claude, Benjamin J. Scott, Kyumsung Lee, Stephen H. Perlmutter
  • Publication number: 20190377674
    Abstract: A data storage device can be arranged with a semiconductor memory having a plurality of erasure blocks accessed by a controller to store data. An access count for each respective erasure block can be generated to allow a wear range for the semiconductor memory to be computed based on the respective access counts with the controller. A performance impact of the wear range is evaluated with the controller in order to intelligently alter a deterministic window of a first erasure block of the plurality of erasure blocks in response to the performance impact.
    Type: Application
    Filed: January 31, 2019
    Publication date: December 12, 2019
    Inventors: Stephen H. Perlmutter, Kyumsung Lee
  • Publication number: 20190377633
    Abstract: Apparatus and method for storing data in a non-volatile memory (NVM), such as a flash memory in a solid-state drive (SSD). In some embodiments, a distributed storage space of the NVM is defined to extend across a plural number of regions of the NVM. A non-standard parity data set is provided having a plural number of data elements greater than or equal to the plural number of regions in the storage space. The data set is written by storing a first portion of the data elements and a first parity value to the plural number of regions and a remaining portion of the data elements and a second parity value to a subset of the plural number of regions. The regions can comprise semiconductor dies in a flash memory, and the distributed storage space can be a garbage collection unit formed using one erasure block from each flash die.
    Type: Application
    Filed: December 6, 2018
    Publication date: December 12, 2019
    Inventors: Stephen H. Perlmutter, Steven S. Williams, Benjamin J. Scott, Andrew J. Louder, Kyumsung Lee, Robert W. Dixon
  • Publication number: 20190378589
    Abstract: A data storage system can receive a data write request to write data to a physical address of a non-volatile semiconductor memory prior to detecting an error while storing the write data to the physical address. The detected error is corrected with a monitor module connected to the non-volatile semiconductor memory and a counter associated with the physical address is incremented with the monitor module in response to the corrected error. The write data can be subsequently read to a host in response to a data read request.
    Type: Application
    Filed: January 31, 2019
    Publication date: December 12, 2019
    Inventor: Stephen H. Perlmutter
  • Patent number: 7379144
    Abstract: An optical device includes a ferroelectric liquid crystal material. This optical device has a first and a second substrate. A first alignment treatment is applied to a surface of the first substrate, the first alignment treatment being intended to induce an orientation of at least a portion of the ferroelectric liquid crystal material along a first alignment direction with a first pretilt angle ?1 with respect to a plane parallel to the first substrate. A second alignment treatment is applied to a surface of the second substrate, the second alignment treatment being intended to induce an orientation of at least another portion of the ferroelectric liquid crystal material along a second alignment direction with a second pretilt angle ?2 with respect to a plane parallel to the second substrate.
    Type: Grant
    Filed: June 9, 2000
    Date of Patent: May 27, 2008
    Assignee: Displaytech, Inc.
    Inventors: Jiuzhi Xue, Beth L. Ellis, Stephen H. Perlmutter, Charles Crandall