Abstract: A digital system is provided with an interface circuit for interconnecting two modules in different clock domains. The interface circuit can selectively respond to a request signal from a remote source and immediately de-assert a ready signal in response to either a rising edge or a falling edge of the request signal asynchronously to a local clock signal. When an internal circuit connected to the interface circuit has completed a requested operation, the interface circuit asserts the ready signal. The ready signal is de-asserted and asserted in a glitchless manner so that the remote module can respond to the ready signal asynchronously to a remote clock signal.