Abstract: Bias circuit elements for applying voltages/currents to a photodetector are described. Bias circuit elements described are active devices, e.g. mosfets, directly connected to the photodetector signal point, which inject noise that will be amplified/integrated. Lowering 1/f noise in these bias devices uses multiple parallel mosfets and switching the parallel mosfets gates between a bias activation level signal and a voltage sufficient to drive the mosfet into accumulation Gate switching may be accomplished by at least two partially out of phase clocking signals, with at least one parallel mosfet applying bias while another is in accumulation in continuously switched time periods. Gate switching at a frequency higher than the imaging bandwidth, will have negligible effect on the image signal. During the accumulation phase traps present within the conducting channel of each MOSFET will be depopulated, essentially resetting the MOSFET's 1/f noise, allowing for long integration times while controlling 1/f noise.

Abstract: A photodetector interface circuit is described, residing partially or fully within a unit cell per pixel of an FPA. The interface circuit uses an innovative approach to providing pixel level digitization for full frame integration times while maintaining the ability to use integration capacitors of practical sizes. The technique uses successive charge subtraction, removing charge from an integration capacitor successively, triggered by the charge increasing sufficiently to charge the integrator to a reference level, thereby triggering both charge removal and incrementing a count, until all of the current flowing in the photodetector has been accounted for and the count represents the digitization of the photodetector signal. Various options on how to arrange the digitization elements are also disclosed.

Abstract: A photodetector interface circuit is described, residing partially or fully within a unit cell per pixel of an FPA. The interface circuit uses an innovative approach to providing pixel level digitization for full frame integration times while maintaining the ability to use integration capacitors of practical sizes. The technique uses successive charge subtraction, removing charge from an integration capacitor successively, triggered by the charge increasing sufficiently to charge the integrator to a reference level, thereby triggering both charge removal and incrementing a count, until all of the current flowing in the photodetector has been accounted for and the count represents the digitization of the photodetector signal. Various options on how to arrange the digitization elements are also disclosed.

Abstract: Bias circuit elements for applying voltages/currents to a photodetector are described. Bias circuit elements described are active devices, e.g. mosfets, directly connected to the photodetector signal point, which inject noise that will be amplified/integrated. Lowering 1/f noise in these bias devices uses multiple parallel mosfets and switching the parallel mosfets gates between a bias activation level signal and a voltage sufficient to drive the mosfet into accumulation Gate switching may be accomplished by at least two partially out of phase clocking signals, with at least one parallel mosfet applying bias while another is in accumulation in continuously switched time periods. Gate switching at a frequency higher than the imaging bandwidth, will have negligible effect on the image signal. During the accumulation phase traps present within the conducting channel of each MOSFET will be depopulated, essentially resetting the MOSFET's 1/f noise, allowing for long integration times while controlling 1/f noise.