Abstract: A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame's destination is a virtual entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction.

Abstract: A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame's destination is a virtual entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction.

Abstract: A transport stream decoder/demultiplexer is provided which includes a program clock recovery circuit for recovering a program clock from program clock reference (PCR) values contained in selected transport packets. A processor is provided for extracting elementary stream data from transport packets labeled with packet identification codes (PIDs) that are specified by a host processor. The processor separately stores the elementary stream data of each stream. A host processor interface is also provided for transferring data between an external host processor and the program clock recovery circuit. A memory manager may be provided for storing the data extracted by the processor for each elementary stream in a corresponding queue. The queues may be maintained by the memory manager in an external RAM. A descrambler interface may be provided for transferring scrambled data and data derived from conditional access information between the processor and an external descrambler.

Abstract: The invention comprises apparatus for determining the orientation of the crystallographic axes of a single crystal. The crystal is rotated on a turntable while an X-ray beam containing characteristic radiation is directed onto it. A stationary position-sensitive detector, preferably positioned at right angles to the beam detects Bragg reflections from the crystal, and computing means responsive to the signals from the detector, and signals representing the angular position of the turntable determines the crystal orientation.

Abstract: The invention comprises a method of, and apparatus for, measuring the orientation error in a single crystal. An X-ray beam is reflected from the surface of the crystal while it is rotated, and the orientation error is determined from the figure traced at a detector by the reflected beam. The orientation error may be calculated from the major axes of the traced figure, or, if the X-ray beam contains a characteristic line, from the separation of the two bright spots produced in the traced figure.