Abstract: A method of non-invasive insertion of logic functions into a register-transfer level (RTL) design, including: selecting a logic function to insert into a RTL design; identifying each hierarchical level executing at least a portion of the logic function; identifying a highest hierarchical level amongst hierarchical levels having each hierarchical level executing at least a portion of the logic function; and inserting all connections necessary to execute the logic function into a hardware description representation of the highest hierarchical level, without modifying a hardware description representation of any other hierarchical levels.

Abstract: Non-invasive insertion of logic functions into a RTL design, including: selecting a logic function to insert into an RTL design; identifying each hierarchical level executing at least a portion of the logic function; identifying a highest hierarchical level amongst each hierarchical level executing at least a portion of the logic function; and inserting all connections necessary to execute the logic function into a hardware description representation of the highest hierarchical level, without modifying a hardware description representation of any other hierarchical levels.

Abstract: A method, system and computer program product for modeling and simulating a powergated hierarchical element of an integrated circuit is disclosed. In modeling a powergated macro, the invention does not model all logic gates or elements as powergated, instead, the invention only models latches as connected to an integrated switch to be powergated. In addition, a fence circuit attached to the powergated macro is modeled as including an extra control signal to force a powergated state of the powergated macro into the fence circuit.