Patents by Inventor Stephen J. Burden

Stephen J. Burden has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7119400
    Abstract: A semiconductor wafer structure having a device layer, an insulating layer, and a substrate which is capable of supporting increased semiconductor device densities or increased semiconductor device power. One or more of the layers includes an isotopically enriched semiconductor material having a higher thermal conductivity than semiconductor material having naturally occurring isotopic ratios. The wafer structure may be formed by various techniques, such as wafer bonding, and deposition techniques.
    Type: Grant
    Filed: December 24, 2003
    Date of Patent: October 10, 2006
    Assignee: Isonics Corporation
    Inventor: Stephen J. Burden
  • Patent number: 6867459
    Abstract: The present invention provides improved semiconductor wafer structures having isotopically-enriched layers and methods of making the same.
    Type: Grant
    Filed: July 3, 2002
    Date of Patent: March 15, 2005
    Assignee: Isonics Corporation
    Inventor: Stephen J. Burden
  • Publication number: 20040169225
    Abstract: A semiconductor wafer structure having a device layer, an insulating layer, and a substrate which is capable of supporting increased semiconductor device densities or increased semiconductor device power. One or more of the layers includes an isotopically enriched semiconductor material having a higher thermal conductivity than semiconductor material having naturally occurring isotopic ratios. The wafer structure may be formed by various techniques, such as wafer bonding, and deposition techniques.
    Type: Application
    Filed: December 24, 2003
    Publication date: September 2, 2004
    Inventor: Stephen J. Burden
  • Publication number: 20040171226
    Abstract: A semiconductor wafer structure having a device layer, an insulating layer, and a substrate which is capable of supporting increased semiconductor device densities or increased semiconductor device power. One or more of the layers includes an isotopically enriched semiconductor material having a higher thermal conductivity than semiconductor material having naturally occurring isotopic ratios. The insulating layer may be formed by implanting atoms or ions into a semiconductor layer and subjecting the wafer to heat treatment resulting in the implanted atoms or ions reacting with the semiconductor layer to form an insulating layer.
    Type: Application
    Filed: December 24, 2003
    Publication date: September 2, 2004
    Inventor: Stephen J. Burden
  • Patent number: 6653658
    Abstract: The invention is directed to semiconductor wafer structures having increased thermal conductivity over conventional semiconductor wafer designs due to the inclusion of an isotopically-enriched material on at least one surface of the wafer substrate. The isotopically-enriched material may be isotopically-enriched silicon, germanium, silicon-germanium alloys, gallium arsenide, aluminum gallium arsenide, gallium nitride, gallium phosphide, gallium indium nitride, indium phosphide or combinations and alloys of these materials. In another embodiment, the substrate is removed from the wafer structure to leave a top semiconductor layer on a layer of isotopically-enriched materials with no underlying substrate.
    Type: Grant
    Filed: July 3, 2002
    Date of Patent: November 25, 2003
    Assignee: Isonics Corporation
    Inventor: Stephen J. Burden
  • Publication number: 20030039865
    Abstract: The present invention is directed to isotopically enriched optical materials and methods of producing the same. The optical materials provide high isotopic purity silica, calcium, zinc, gallium and germanium materials with increased resistance to optical damage which can be used alone or in combination with other means of preventing damage to decrease lens degradation caused by energy-induced compaction during use.
    Type: Application
    Filed: June 20, 2002
    Publication date: February 27, 2003
    Applicant: Isonics Corporation
    Inventors: Vic Kelsey, James E. Alexander, Stephen J. Burden
  • Publication number: 20030013275
    Abstract: The present invention provides improved semiconductor wafer structures having isotopically-enriched layers and methods of making the same.
    Type: Application
    Filed: July 3, 2002
    Publication date: January 16, 2003
    Inventor: Stephen J. Burden
  • Publication number: 20030010978
    Abstract: The invention is directed to semiconductor wafer structures having increased thermal conductivity over conventional semiconductor wafer designs due to the inclusion of an isotopically-enriched material on at least one surface of the wafer substrate. The isotopically-enriched material may be isotopically-enriched silicon, germanium, silicon-germanium alloys, gallium arsenide, aluminum gallium arsenide, gallium nitride, gallium phosphide, gallium indium nitride, indium phosphide or combinations and alloys of these materials. In another embodiment, the substrate is removed from the wafer structure to leave a top semiconductor layer on a layer of isotopically-enriched materials with no underlying substrate.
    Type: Application
    Filed: July 3, 2002
    Publication date: January 16, 2003
    Inventor: Stephen J. Burden
  • Patent number: 4652276
    Abstract: A silicon nitride cutting tool primarily for cutting cast iron comprises a granular phase consisting essentially of silicon nitride and an intergranular amorphous phase consisting essentially of magnesium oxide, yttrium oxide and silicon oxide wherein the components are present in specified amounts and ratios.
    Type: Grant
    Filed: March 10, 1986
    Date of Patent: March 24, 1987
    Assignee: GTE Valeron Corporation
    Inventor: Stephen J. Burden
  • Patent number: 4452906
    Abstract: Improved ceramic compositions useful for cutting tools and the like are described. They are composed of an essentially homogeneous admixture of sintered powders of an aluminum oxide base material with other refractories including zirconium oxide, titanium oxide, hafnium oxide, titanium nitride, zirconium nitride, and tungsten or molybdenum carbide. In addition to their common and improved properties of hardness and strength, many of these compositions may be made by simple cold-pressing and sintering procedures. This avoids the known drawbacks of conventional hot press production.
    Type: Grant
    Filed: February 3, 1983
    Date of Patent: June 5, 1984
    Inventor: Stephen J. Burden
  • Patent number: 4396724
    Abstract: Improved ceramic compositions useful for cutting tools and the like are described. They are composed of an essentially homogeneous admixture of sintered powders of an aluminum oxide base material with other refractories including zirconium oxide, titanium oxide, hafnium oxide, titanium nitride, zirconium nitride, and tungsten or molybdenum carbide. In addition to their common and improved properties of hardness and strength, many of these compositions may be made by simple cold-pressing and sintering procedures. This avoids the known drawbacks of conventional hot press production.
    Type: Grant
    Filed: May 26, 1981
    Date of Patent: August 2, 1983
    Assignee: General Electric Co.
    Inventor: Stephen J. Burden
  • Patent number: 4257809
    Abstract: A process for forming a WC-Mo C solid solution alloy starts by first intensely milling, such as dry attritor milling, Mo and W metal powders, followed by a homogenization heat treatment of about 1400.degree. to 1500.degree. C. to form an Mo-W solid solution alloy. The Mo-W solid solution alloy is then crushed to form a fine powder and mixed by ball milling with the appropriate amount of carbon plus cobalt. The milled alloy powder is then heated at approximately 1100.degree. to 1400.degree. C. to form the desired WC-Mo C alloy.
    Type: Grant
    Filed: January 5, 1979
    Date of Patent: March 24, 1981
    Assignee: General Electric Company
    Inventor: Stephen J. Burden