Abstract: An LDMOSFET transistor (100) is provided which includes a substrate (101), an epitaxial drift region (104) in which a drain region (116) is formed, a first well region (107) in which a source region (112) is formed, a gate electrode (120) formed adjacent to the source region (112) to define a first channel region (14), and a grounded substrate injection suppression guard structure that includes a patterned buried layer (102) in ohmic contact with an isolation well region (103) formed in a predetermined upper region of the substrate so as to be spaced apart from the first well region (107) and from the drain region (116), where the buried layer (102) is disposed below the first well region (107) but not below the drain region (116).

Abstract: An LDMOSFET transistor (100) is provided which includes a substrate (101), an epitaxial drift region (104) in which a drain region (116) is formed, a first well region (107) in which a source region (112) is formed, a gate electrode (120) formed adjacent to the source region (112) to define a first channel region (14), and a grounded substrate injection suppression guard structure that includes a patterned buried layer (102) in ohmic contact with an isolation well region (103) formed in a predetermined upper region of the substrate so as to be spaced apart from the first well region (107) and from the drain region (116), where the buried layer (102) is disposed below the first well region (107) but not below the drain region (116).

Abstract: A substantially planar semiconductor surface is formed for fabricating submicron BiCMOS integrated circuits. A lightly doped epitaxial layer is formed on a semiconductor substrate having buried layers formed therein. The substantially planar semiconductor surface is formed by forming a p-type well in the lightly doped epitaxial layer before the step of forming an n-type well in the lightly doped epitaxial layer.

Abstract: An improved bipolar transistor of a BiCMOS integrated circuit is fabricated by utilizing a nitride layer combined with two polysilicon layers to form a self-aligned P-type extrinsic base which results in lower base resistance and lower base-collector capacitance, and thus improved performance.

Abstract: An improved bipolar transistor of a BiCMOS integrated circuit is fabricated by utilizing a nitride layer over a thin silicon dioxide layer combined with a polysilicon layer. This bipolar structure has a self-aligned, P-type extrinsic base which results in lower base resistance and improved performance.

Abstract: A process of forming a conductive material layer in at least two steps by forming a conductive material layer from a plurality of thin layers of conductive material. The use of a two-step formation process for the conductive material layer permits process versatility in incorporating implantation steps and patterning steps between formation of the thin layers of conductive material. Direct transfer from dielectric layer formation to conductive material layer formation steps, and performing the intermediate process steps in the same piece of equipment as the thin conductive layer formation assists in adhesion of the thin layers to each other to form the total conductive material layer. The use of in situ doped semiconductor material, such as in situ doped polycrystalline silicon and in situ doped amorphous silicon reduces the exposure of other dopants that may be present to thermal cycles of high temperature, greater than 900.degree. C., that causes these dopants to migrate undesirably.

Abstract: A method of using removable sidewall spacers to minimize the need for mask levels in forming lightly doped drains (LDDs) in the formation of CMOS integrated circuits. Aluminum or chemical vapor deposition (CVD) metals such as tungsten are suitable materials to form removable sidewall spacers which exist around CMOS gates during heavily doped source/drain region implants. Other materials such as CVD polysilicon may also be useful for the sidewall spacers. The sidewall spacers are removed before implantation of the lightly doped drain regions around the gates. This implanation sequence is exactly the reverse of what is currently practiced for lightly doped drain formation. The invention also includes the use of a differential oxide layer. A second set of disposable sidewall spacers or the use of permanent sidewall spacers form optional embodiments.

Abstract: A method of using removable sidewall spacers to minimize the need for mask levels in forming lightly doped drains (LDDS) in the formation of CMOS integrated circuits. Aluminum or chemical vapor deposition (CVD) metals such as tungsten are suitable materials to form removable sidewall spacers which exist around CMOS gates during heavily doped source/drain region implants. Conformal materials such as CVD polysilicon may also be employed for this purpose. The sidewall spacers are removed before implantation of the lightly doped drain regions around the gates. This implantation sequence is exactly the reverse of what is currently practiced for lightly doped drain formation.

Abstract: A process is disclosed for fabricating complementary insulated gate field effect transistors including doped field isolation regions and optional punch through protection. In one embodiment of invention, a silicon substrate is provided which has N-type and P-type surface regions. First and second masks are formed overlying active areas of the two surface regions. A third mask is then formed overlying the first region and the first mask. P-type impurities are implanted into the second region with an implant energy which is sufficient to penetrate through the second mask but insufficient to penetrate through the third mask. A second P-type implant is performed with an implant energy insufficient to penetrate through either mask. The first implant will aid in preventing punch through while the second implant dopes the field region. A fourth mask is then formed overlying the second region and the second mask.

Abstract: A deep, buried n.sup.- channel blanket implant beneath both n.sup.- channel and p-channel devices in MOS integrated circuits, whether complementary MOS (CMOS) or not. It is known to use deep, lightly-doped n.sup.- channel implant to improve the characteristics of p-channel (PMOS) devices, although one skilled in the art would expect such an n.sup.- implant to be detrimental to n-channel (NMOS) devices. It has been discovered that such implants not only do not degrade the NMOS devices, but in fact improve their performance, with respect to body effect and junction capacitance.