Abstract: A method for insuring data consistency between a plurality of individual processor cache memories and the main memory in a multi-processor computer system is provided which is capable of (1) detecting when one of a set of predefined data inconsistency states occurs as a data transaction request is being processed, and (2) correcting the data inconsistency states so that the operation may be executed in a correct and consistent manner.

Abstract: All monitoring and control of locked memory access requests in a multiprocessing computer system is handled by a system control unit (SCU) which controls the parallel operation of a plurality of central processing units (CPUs) and I/O units relative to a common main memory. Locking granularity is defined at the level of individual cache blocks for the CPUs, and the cache blocks also represent the unit of memory allocation in the computer system. The SCU is provided with a lock directory defined by a plurality of lock bits so that addresses in the same block of memory are mapped to the same location in the lock directory. Incoming lock requests for a given memory location are processed by interrogating the corresponding lock bit in the lock directory in the SCU by using the associated memory address as an index into the directory. If the lock bit is not set, the lock request is granted.

Abstract: In a data storage unit, internal timing signals are produced by scanning a writable control memory. Thus, the timing of the storage unit can easily be varied, simply by re-writing the contents of the control memory. This allows the use of a faster clock rate without the necessity for complete redesign of the storage unit. The basic clock period is sub-divided into a number of sub-periods, allowing the timing signals to be adjusted with an accuracy better than one clock period.