Patents by Inventor Stephen J. Powell
Stephen J. Powell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11687254Abstract: One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communications links in a memory system. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. In one embodiment, the Host only transmits data (and CRC) and does not transmit control signals, over its communications link with the data buffer circuits. In one aspect, the memory control circuit does not send the store data tag to the data buffer circuits. In one embodiment, the Host and the data buffer circuits each maintain a separate state machine-driven address pointer or local address sequencer, e.g., local store tag FIFO, which contains the same tags in the same sequence. A periodic system check and resynchronization method is also disclosed.Type: GrantFiled: November 7, 2019Date of Patent: June 27, 2023Assignee: International Business Machines CorporationInventors: Steven R. Carlough, Susan M. Eickhoff, Patrick J. Meaney, Stephen J. Powell, Gary A. Van Huben, Jie Zheng
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Patent number: 11587600Abstract: One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communication links. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. The memory system, architectural structure and/or method improves the ability of the communications links to transfer data downstream to the data buffer circuits. The memory control circuit receives a store command and a store data tag (Host tag) from a Host and sends the store data command and the store data tag to the data buffer circuits. No store data tag or control signal is sent over the communication links between the Host and the data buffer circuits, only data is sent over the communication links between the Host and the data buffer circuits.Type: GrantFiled: April 29, 2019Date of Patent: February 21, 2023Assignee: International Business Machines CorporationInventors: Steven R. Carlough, Susan M. Eickhoff, Warren E. Maule, Patrick J. Meaney, Stephen J. Powell, Gary A. Van Huben, Jie Zheng
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Patent number: 11520659Abstract: A computer-implemented method includes refreshing a set of memory channels in a memory system substantially simultaneously, each memory channel refreshing a rank that is distinct from each of the other ranks being refreshed. Further, the method includes marking a memory channel from the set of memory channels as being unavailable for the rank being refreshed in the memory channel. In one or more examples, the method further includes blocking a fetch command to the memory channel for the rank being refreshed in the memory channel.Type: GrantFiled: January 13, 2020Date of Patent: December 6, 2022Assignee: International Business Machines CorporationInventors: Patrick James Meaney, Glenn David Gilda, David D. Cadigan, Christian Jacobi, Lawrence Jones, Stephen J. Powell
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Patent number: 11379123Abstract: One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communications links in a memory system. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. In one embodiment, the Host only transmits data over its communications link with the data buffer circuit. In one aspect, the memory control circuit does not send a control signal to the data buffer circuits. In one aspect, the memory control circuit and the data buffer circuits each maintain a separate state machine-driven address pointer or local address sequencer, which contains the same tags in the same sequence. In another aspect, a resynchronization method is disclosed.Type: GrantFiled: March 5, 2021Date of Patent: July 5, 2022Assignee: International Business Machines CorporationInventors: Steven R. Carlough, Susan M. Eickhoff, Patrick J. Meaney, Stephen J. Powell, Gary A. Van Huben, Jie Zheng
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Patent number: 11372703Abstract: A memory controller receives, via a first interface, a first read request requesting a requested data granule. Based on receipt of the first read request, the memory controller transmits, via a second interface, a second read request to initiate access of the requested data granule from a system memory. Based on a determination to schedule accelerated data delivery and receipt by the memory controller of a data scheduling indication that indicates a timing of future delivery of the requested data granule, the memory controller requests, prior to receipt of the requested data granule, permission to transmit the requested data granule on the system interconnect fabric. Based on receipt of the requested data granule at the indicated timing and a grant of the permission to transmit, the memory controller initiates transmission of the requested data granule on the system interconnect fabric and transmits an error indication for the requested data granule.Type: GrantFiled: February 19, 2021Date of Patent: June 28, 2022Assignee: International Business Machines CorporationInventors: John Samuel Liberty, Brad William Michael, Stephen J. Powell, Nicholas Steven Rolfe
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Patent number: 11269561Abstract: A system and associated processes may perform a memory access operation that includes receiving a data packet comprising a command of a type of a plurality of types of commands. The processes may include initiating a decoding of a first portion of the command, and automatically speculating as to the type of the command. Based on the speculation as to the type of the command, a bank activate command may be generated before the data packet is entirely decoded or received.Type: GrantFiled: December 21, 2020Date of Patent: March 8, 2022Assignee: International Business Machines CorporationInventors: Jie Zheng, Steven R. Carlough, William J. Starke, Jeffrey A. Stuecheli, Stephen J. Powell
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Patent number: 11157411Abstract: An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. When the L2 cache memory finishes servicing the interrupting load request, the L2 cache memory may return to servicing the interrupted store request at the point of interruption.Type: GrantFiled: November 22, 2019Date of Patent: October 26, 2021Assignee: International Business Machines CorporationInventors: Sanjeev Ghai, Guy L. Guthrie, Stephen J. Powell, William J. Starke
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Publication number: 20210216401Abstract: A computer-implemented method includes refreshing a set of memory channels in a memory system substantially simultaneously, each memory channel refreshing a rank that is distinct from each of the other ranks being refreshed. Further, the method includes marking a memory channel from the set of memory channels as being unavailable for the rank being refreshed in the memory channel. In one or more examples, the method further includes blocking a fetch command to the memory channel for the rank being refreshed in the memory channel.Type: ApplicationFiled: January 13, 2020Publication date: July 15, 2021Inventors: PATRICK JAMES MEANEY, GLENN DAVID GILDA, DAVID D. CADIGAN, CHRISTIAN JACOBI, LAWRENCE JONES, STEPHEN J. POWELL
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Publication number: 20210191630Abstract: One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communications links in a memory system. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. In one embodiment, the Host only transmits data over its communications link with the data buffer circuit. In one aspect, the memory control circuit does not send a control signal to the data buffer circuits. In one aspect, the memory control circuit and the data buffer circuits each maintain a separate state machine-driven address pointer or local address sequencer, which contains the same tags in the same sequence. In another aspect, a resynchronization method is disclosed.Type: ApplicationFiled: March 5, 2021Publication date: June 24, 2021Inventors: Steven R. Carlough, Susan M. Eickhoff, Patrick J. Meaney, Stephen J. Powell, Gary A. Van Huben, Jie Zheng
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Patent number: 11042325Abstract: A system and associated processes may perform a memory access operation that includes receiving a data packet comprising a command of a type of a plurality of types of commands. The processes may include initiating a decoding of a first portion of the command, and automatically speculating as to the type of the command. Based on the speculation as to the type of the command, a bank activate command may be generated before the data packet is entirely decoded or received.Type: GrantFiled: August 5, 2019Date of Patent: June 22, 2021Assignee: International Business Machines CorporationInventors: Jie Zheng, Steven R. Carlough, William J. Starke, Jeffrey A. Stuecheli, Stephen J. Powell
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Patent number: 11042312Abstract: A system, method, and computer program product are provided herein to manage DRAM bank activation per cycle. A memory controller with embedded scheduling logic is employed to manage the system, method, and computer program product and to restrict the quantity of active banks in a given cycle, resulting in power savings with minimal performance loss, if any. The scheduling logic provides instructions to manage the state of associated DRAM banks. Each bank is either in an idle state or an active state, with the idle state consuming less power than the active state. The scheduling logic restricts the quantity of active banks in any cycle, with all other banks being in an idle state, which provides power savings to the associated system.Type: GrantFiled: August 22, 2019Date of Patent: June 22, 2021Assignee: International Business Machines CorporationInventors: Dharmesh Parikh, Stephen J. Powell, Venkata K. Tavva
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Publication number: 20210109680Abstract: A system and associated processes may perform a memory access operation that includes receiving a data packet comprising a command of a type of a plurality of types of commands. The processes may include initiating a decoding of a first portion of the command, and automatically speculating as to the type of the command. Based on the speculation as to the type of the command, a bank activate command may be generated before the data packet is entirely decoded or received.Type: ApplicationFiled: December 21, 2020Publication date: April 15, 2021Inventors: Jie ZHENG, Steven R. CARLOUGH, William J. STARKE, Jeffrey A. STUECHELI, Stephen J. POWELL
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Patent number: 10976939Abstract: One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communications links in a memory system. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. In one embodiment, the Host only transmits data over its communications link with the data buffer circuit. In one aspect, the memory control circuit does not send a control signal to the data buffer circuits. In one aspect, the memory control circuit and the data buffer circuits each maintain a separate state machine-driven address pointer or local address sequencer, which contains the same tags in the same sequence. In another aspect, a resynchronization method is disclosed.Type: GrantFiled: October 10, 2019Date of Patent: April 13, 2021Assignee: International Business Machines CorporationInventors: Steven R. Carlough, Susan M. Eickhoff, Patrick J. Meaney, Stephen J. Powell, Gary A. Van Huben, Jie Zheng
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Publication number: 20210042058Abstract: A system and associated processes may perform a memory access operation that includes receiving a data packet comprising a command of a type of a plurality of types of commands. The processes may include initiating a decoding of a first portion of the command, and automatically speculating as to the type of the command. Based on the speculation as to the type of the command, a bank activate command may be generated before the data packet is entirely decoded or received.Type: ApplicationFiled: August 5, 2019Publication date: February 11, 2021Applicants: International Business Machines Corporation, International Business Machines CorporationInventors: Jie ZHENG, Steven R. CARLOUGH, William J. STARKE, Jeffrey A. STUECHELI, Stephen J. POWELL
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Patent number: 10747442Abstract: One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communication links. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. In one aspect, the data buffer circuit receives a next to be used store data tag from a Host wherein the store data tag specifies the data buffer location in the data buffer circuit to store data, and in response to receiving store data from the Host, moves the data received at the data buffer circuit into the data buffer pointed to by the previously received store data tag.Type: GrantFiled: November 29, 2017Date of Patent: August 18, 2020Assignee: International Business Machines CorporationInventors: Steven R. Carlough, Susan M. Eickhoff, Warren E. Maule, Patrick J. Meaney, Stephen J. Powell, Gary A. Van Huben, Jie Zheng
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Patent number: 10740031Abstract: An Address and Command chip of a distributed memory system includes a memory controller, a first communication link, and one or more interface schedulers, where the one or more interface schedulers include a first interface scheduler residing communicatively between the memory controller and the first communication link. The first interface scheduler is configured to receive a first communication directed from the memory controller to the first communication link; capture the first communication before the first command reaches the first communication link; postpone the first communication for a first set of one or more memory cycles; and reissue the first communication to the first communication link in association with a first cycle offset code indicating how many memory cycles the first command was postponed.Type: GrantFiled: September 25, 2018Date of Patent: August 11, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jie Zheng, Stephen J. Powell, Steven R. Carlough, Susan M. Eickhoff
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Publication number: 20200110704Abstract: An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. When the L2 cache memory finishes servicing the interrupting load request, the L2 cache memory may return to servicing the interrupted store request at the point of interruption.Type: ApplicationFiled: November 22, 2019Publication date: April 9, 2020Inventors: Sanjeev Ghai, Guy L. Guthrie, Stephen J. Powell, William J. Starke
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Publication number: 20200097214Abstract: An Address and Command chip of a distributed memory system includes a memory controller, a first communication link, and one or more interface schedulers, where the one or more interface schedulers include a first interface scheduler residing communicatively between the memory controller and the first communication link. The first interface scheduler is configured to receive a first communication directed from the memory controller to the first communication link; capture the first communication before the first command reaches the first communication link; postpone the first communication for a first set of one or more memory cycles; and reissue the first communication to the first communication link in association with a first cycle offset code indicating how many memory cycles the first command was postponed.Type: ApplicationFiled: September 25, 2018Publication date: March 26, 2020Inventors: Jie Zheng, Stephen J. Powell, Steven R. Carlough, Susan M. Eickhoff
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Publication number: 20200073565Abstract: One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communications links in a memory system. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. In one embodiment, the Host only transmits data (and CRC) and does not transmit control signals, over its communications link with the data buffer circuits. In one aspect, the memory control circuit does not send the store data tag to the data buffer circuits. In one embodiment, the Host and the data buffer circuits each maintain a separate state machine-driven address pointer or local address sequencer, e.g., local store tag FIFO, which contains the same tags in the same sequence. A periodic system check and resynchronization method is also disclosed.Type: ApplicationFiled: November 7, 2019Publication date: March 5, 2020Inventors: Steven R. Carlough, Susan M. Eickhoff, Patrick J. Meaney, Stephen J. Powell, Gary A. Van Huben, Jie Zheng
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Patent number: 10572168Abstract: A system, method, and computer program product are provided herein to manage DRAM bank activation per cycle. A memory controller with embedded scheduling logic is employed to manage the system, method, and computer program product and to restrict the quantity of active banks in a given cycle, resulting in power savings with minimal performance loss, if any. The scheduling logic provides instructions to manage the state of associated DRAM banks. Each bank is either in an idle state or an active state, with the idle state consuming less power than the active state. The scheduling logic restricts the quantity of active banks in any cycle, with all other banks being in an idle state, which provides power savings to the associated system.Type: GrantFiled: November 16, 2017Date of Patent: February 25, 2020Assignee: International Business Machines CorporationInventors: Dharmesh Parikh, Stephen J. Powell, Venkata K. Tavva