Abstract: A pipelined computer which process operand data through a sequence of D,A,T,B,X and W stages includes a sidetrack queue. Data which exits the B stage prematurely, before the X stage is ready to immediately process such data, is held over in the sidetrack queue and presented to the X stage at a later time. The sidetracking mechanism is used to speed processing of rate-variable operand-consuming instructions such as the EDIT and EDMK commands.

Abstract: A processing system comprising a first means for generating first signals indicating when the next instruction can begin processing where eight or less bytes are processed by the MOVE, PACK or UNPACK instruction, a second means for generating second signals if an overlap condition exists for the MOVE, PACK or UNPACK instruction being processed, and where the first means generates the first signals prior to the second means generating the second signals and independent of whether the second means generates the second signals.

Abstract: A divider, which performs division in a base other than 2, that reduces in most cases the number of cycles it takes to generate each quotient digit. This involves predicting the minimum possible quotient digit in response to leading digits of the partial remainder and of the divisor. The predicted minimum possible quotient digit times the divisor is then subtracted from the partial remainder. If the result of the subtraction is less than the divisor, the predicted least possible quotient digit is the correct quotient digit. If the result of the subtraction is greater than the divisor, the divisor is subtracted iteratively from that result until the partial remainder falls below the value of the divisor. For each subtraction, the predicted quotient digit is incremented by one, so that a correct quotient digit results at the end of the iteration.

Abstract: A microword controlled computer system with an apparatus for performing a pseudo branch. The pseudo branch involves the re-execution of a selected microword in a microword register. The computer system comprises a microword register, N control stores, an apparatus for selectively transferring a microword from one of the N control stores to the microword register, an apparatus coupled to said microword register for executing each microword in said microword register and an apparatus for branching to N+1 targets wherein each one of N of said N+1 targets comprises a microword from one of said N control stores and one of said N+1 targets is a current microword in said microword register.

Abstract: In a floating point arithmetic unit, high speed computation is achieved by providing logic for determining whether operands of an instruction have a predetermined condition with respect to the instruction and logic responsive thereto for bypassing selective primitive operations when such predetermined condition exists.

Abstract: Dedicated convert hardware is disclosed for performing bidirectional conversions of numbers between binary and another base b (illustratively decimal) for use in a data processing system. The dedicated convert hardware comprises a special purpose multiply-and-add unit and a convert register. The output of the multiply-and-add unit is coupled to the input of the convert register, and the output of the convert register is recycled to the inputs of the multiply-and-add unit. The multiply-and-add unit is hardwired to multiply the input by b and concurrently add the value at a separate digit input. Means are also provided for initializing the convert register with zero or with any desired number.

Abstract: An instruction execution unit receives instructions and, in turn, provides a sequence of control words to specify the sequential processing of the operand data provided with the instruction. A sequencer nominally issues a first sequence of control words corresponding to the instruction. The sequencer includes a sequence selector for selecting a second sequence of control words for issuance by the sequencer. Control logic is provided to determine from the operand data, concurrent with the issuance of at least the first issued control word, whether the operand data is ideal with respect to the instruction, where ideal is defined as the predicted nonoccurence of underflow and overflow conditions. On determining that the operand data is ideal with respect to the instruction, the sequence selector is caused to select the second sequence of control words for issuance.

Abstract: Disclosed is a signed multiplier for use in a data processing system that handles 2's complement operands. The signed multiplier operates to form a preliminary product independently of the signs of the multiplier and multiplicand. While the multiplication is in progress, the signs of the multiplier and multiplicand are checked. For multiplications where either one of the operands (multiplier or multiplicand) is negative, the preliminary product is modified by one or two correction factors. The correction factors are multiplies of the 2's complements of the operands. The correction factor or factors are added to the preliminary product to form the final product.

Abstract: In dividing a pair of binary coded, hexidecimal floating point numbers, leading zero quotient bits are eliminated by comparing the magnitudes of the most significant digits of the fractional parts of the dividend and divisor after the dividend and divisor have been normalized.

Abstract: An ancillary execution unit is interfaced to a primary execution unit of a data processing system where the ancillary unit operates faster than the primary for certain instructions and allows for bypassing the slower unit. The primary execution unit has an instruction input receiving an instruction, an operand input receiving data and an operand output transferring data from the primary execution unit to the data processing system. The ancillary execution unit obtains the instruction from the instruction input, obtains the data from the operand input, performs the function indicated by the instruction to the data, and returns data to the primary execution unit.

Abstract: A two control store scheme with instruction execution overlay is shown in a data processing system execution unit having a two-state pipeline. The first control store controls the first-stage facilities during the first cycle of instruction execution and points to the initial location of the second control store. The second control store controls the second-state facilities during the final cycle of instruction execution. The second control store also controls the facilities of both stages during the intermeidate cycles of instruction requiring more than two cycles to execute. Because the second control store controls only the second-stage facilities during the final cycle, execution of the first cycle of the following instruction can take place concurrently within the first-stage facilities under the control of the first control store.

Abstract: Disclosed is a method and apparatus for predicting the condition code of a condition-code-setting instruction by comparing operands in a data processing system. An operand comparator includes one or more half-adders to predict carry outs at an early time. The comparator is used in a data processing system which is operative in response to instructions having operation codes for specifying operations to be executed. The instructions also have operand fields for identifying operands to be utilized in connection with executing the instructions.