Abstract: Two translation lookaside buffers may be provided for simpler operation in some embodiments. A hardware managed lookaside buffer may handle traditional operations. A software managed lookaside buffer may be particularly involved in locking particular translations. As a result, the software's job is made simpler since it has a relatively simpler, software managed translation lookaside buffer to manage for locking translations.

Abstract: A processor includes a multi-level cache hierarchy where a lock property is associated with a cache line. The cache line retains the lock property and may move back and forth within the cache hierarchy. The cache line may be evicted from the cache hierarchy after the lock property is removed.

Abstract: A method includes indexing a translation table stored in memory with a first index of a virtual address corresponding to a first memory region size by querying the translation table at first locations associated with the first index. Indexing the translation table with a second index of the virtual address corresponding to a second memory region size by querying the translation table at second locations associated with the second index. The translation table includes translations for mapping address tags of the virtual address to physical addresses. The first index is different than the second index, and the first memory region size is different than the second memory region size.

Abstract: Two translation lookaside buffers may be provided for simpler operation in some embodiments. A hardware managed lookaside buffer may handle traditional operations. A software managed lookaside buffer may be particularly involved in locking particular translations. As a result, the software's job is made simpler since it has a relatively simpler, software managed translation lookaside buffer to manage for locking translations.

Abstract: A method includes indexing a translation table stored in memory with a first index of a virtual address corresponding to a first memory region size by querying the translation table at first locations associated with the first index. Indexing the translation table with a second index of the virtual address corresponding to a second memory region size by querying the translation table at second locations associated with the second index. The translation table includes translations for mapping address tags of the virtual address to physical addresses. The first index is different than the second index, and the first memory region size is different than the second memory region size.

Abstract: In one embodiment, the present invention includes a method of accessing a cache memory to determine whether requested data is present. In this embodiment, the method may include indexing a cache with a first index corresponding to a first memory region size, and indexing the cache with a second index corresponding to a second memory region size. The second index may be used if the requested data is not found using the first index.

Abstract: A processor-based system may include a main processor and a coprocessor. The coprocessor handles instructions that include opcodes specifying a data processing operation to be performed by the coprocessor and a coprocessor identification field for identifying a target coprocessor for coprocessor instructions. Two bits indicate one of four data sizes including a byte (8 bits), a half word (16 bits), a word (32 bits), and a double word (64 bits). Two other bits indicate a saturation type.

Abstract: A processor system having cache array for storing virtual tag information and physical tag information and corresponding comparators associated with the array to determine cache-hits. Information from the virtual tag array and the physical tag array may be accessed together.

Abstract: An apparatus and a system may include a modal property indicator and an access module to receive the modal property indicator and to access a selected location based on a condition of the modal property indicator. An article may include data, which, when accessed, results in a machine performing a method including indicating a processor mode to a memory including a plurality of instructions and predecoding an instruction selected from the plurality of instructions according to the processor mode.

Abstract: A memory management unit (MMU) includes a translation look-aside buffer (TLB) that stores memory access steering data within corresponding TLB entries for use in steering memory access operations.

Abstract: Briefly, in accordance with an embodiment of the invention, an apparatus and method to provide multi-threaded computer processing is provided. The apparatus may include first and second processing units adapted to share a multi-bank cache memory, an instruction pre-decode unit, a multiply-accumulate unit, a coprocessor, and/or a translation lookaside buffer (TLB). The method may include sharing use of a multi-bank cache memory between at least two transaction initiators.

Abstract: An apparatus and a system may include a modal property indicator and an access module to receive the modal property indicator and to access a selected location based on a condition of the modal property indicator. An article may include data, which, when accessed, results in a machine performing a method including indicating a processor mode to a memory including a plurality of instructions and predecoding an instruction selected from the plurality of instructions according to the processor mode.

Abstract: A processor system having cache array for storing virtual tag information and physical tag information and corresponding comparators associated with the array to determine cache-hits. Information from the virtual tag array and the physical tag array may be accessed together.

Abstract: A processor-based system may include a main processor and a coprocessor. The coprocessor handles instructions that include opcodes specifying a data processing operation to be performed by the coprocessor and a coprocessor identification field for identifying a target coprocessor for coprocessor instructions. Two bits indicate one of four data sizes including a byte (8 bits), a half word (16 bits), a word (32 bits), and a double word (64 bits). Two other bits indicate a saturation type.

Abstract: A microprocessor system utilizing an in-circuit emulator (ICE) to aid in testing and debugging by an external emulator. The microprocessor operates in two modes. One mode is emulation mode in which the microprocessor outputs trace information for allowing the emulator to reconstruct microprocessor execution, and the other mode is interrogation mode where the microprocessor ceases emulation mode, and allows the emulator to modify the state of the microprocessor or interrogate it. An ICEBRK signal is provided on the microprocessor to better handle transition from emulation to interrogation mode. An address mark counter and generator is provided to force the microprocessor to automatically issue an address mark message which includes the location of the microprocessor's instruction pointer. An AMCTRL bit may be further provided to allow a human user to selectively inhibit the issuance of an address mark.