Abstract: A transfer switch having a test signal input and first and second ports. The transfer switch includes a first routing switch and first and second port termination switches. The first routing switch has a routing switch input for receiving the test signal input and first and second outputs. Each output is connected to the routing switch input by a first switching element and each output is connected to ground by a second switching element. The first and second port termination switches are connected to the first and second outputs, respectively, of the first routing switch. Each termination switch includes a common-base transistor, and preferably, a Darlington amplifier with feedback. The common-base transistor is connected to the output of the routing switch and the Darlington amplifier has an output connected to a corresponding one of the first and second ports.

Abstract: A transfer switch having a test signal input and first and second ports. The transfer switch includes a first routing switch and first and second port termination switches. The first routing switch has a routing switch input for receiving the test signal input and first and second outputs. Each output is connected to the routing switch input by a first switching element and each output is connected to ground by a second switching element. The first and second port termination switches are connected to the first and second outputs, respectively, of the first routing switch. Each termination switch includes a common-base transistor, and preferably, a Darlington amplifier with feedback. The common-base transistor is connected to the output of the routing switch and the Darlington amplifier has an output connected to a corresponding one of the first and second ports.

Abstract: A high-frequency switch for blocking or transmitting a high frequency input signal. The switch includes a common-base transistor having an emitter, base, and collector, the emitter being connected to an input node and the base being connected to a power rail that is preferably ground. The input node is coupled to the input signal. The present invention utilizes a shunt having a switching element with closed and open states to route the input signal either to the collector of the common-base transistor or to the power rail. The switching element connects the input node to the power rail in the closed state and isolates the input node from the power rail when the switching element is in the open state. The open and closed states are selected by the application of a control signal to the switching element. A bias circuit sets the input node to be at a first bias potential when the switching element is in the open state and a second bias potential when the switching element is in the closed state.

Abstract: A phase locking method and apparatus use an applied drive signal to acquire and maintain phase lock, and to prevent false locking in the presence of spurious signals. Locking signal and spurious signal components of a feedback signal within the feedback path of a phase locked loop are filtered and summed with the drive signal having a frequency offset from the loop's reference signal and an amplitude less than that of the locking signal and greater than that of the spurious signals. The summed signals are limited so that the overall phase of the limited signal is determined by the signal of highest amplitude. When the drive signal amplitude exceeds the amplitude of the filtered locking signal, the phase of the limited signal is determined by the drive signal. When the amplitude of the filtered locking signal exceeds the drive signal amplitude, the phase of the limited signal is determined by the locking signal.