Abstract: Transceiver circuitry in an integrated circuit device includes a receive path including an analog front end for receiving analog signals from an analog transmission path and conditioning the analog signals, and an analog-to-digital converter configured to convert the conditioned analog signals into received digital signals for delivery to functional circuitry, and a transmit path including a digital front end configured to accept digital signals from the functional circuitry and to condition the accepted digital signals, and a digital-to-analog converter configured to convert the conditioned digital signals into analog signals for transmission onto the analog transmission path. At least one of the analog front end and the digital front end introduces distortion and outputs a distorted conditioned signal.

Abstract: Transceiver circuitry in an integrated circuit device includes a receive path including an analog front end for receiving analog signals from an analog transmission path and conditioning the analog signals, and an analog-to-digital converter configured to convert the conditioned analog signals into received digital signals for delivery to functional circuitry, and a transmit path including a digital front end configured to accept digital signals from the functional circuitry and to condition the accepted digital signals, and a digital-to-analog converter configured to convert the conditioned digital signals into analog signals for transmission onto the analog transmission path. At least one of the analog front end and the digital front end introduces distortion and outputs a distorted conditioned signal.

Abstract: Noise caused by and leaking from a transmit signal into a radio-frequency (RF) receive path signal is reduced by forwarding the transmit signal to a first filter or a digital processor and DAC, scaling the transmit signal and approximating the noise, subtracting first and second corrective signals from the RF receive path signal, down-converting a resulting corrected RF receive path signal, filtering the down-converted corrected signal in a second filter, up-converting the filtered corrected signal to create the first corrective signal, and up-converting the filter or DAC output signal to create the second corrective signal. The transmit signal may come from an output of an RF power amplifier, and may be down-converted prior to filtering in the first filter or processing in the digital processor. The second filter may be a series filter or a shunt filter. A radio includes the circuits to perform the above method.

Abstract: Noise caused by and leaking from a transmit signal into a radio-frequency (RF) receive path signal is reduced by forwarding the transmit signal to a first filter or a digital processor and DAC, scaling the transmit signal and approximating the noise, subtracting first and second corrective signals from the RF receive path signal, down-converting a resulting corrected RF receive path signal, filtering the down-converted corrected signal in a second filter, up-converting the filtered corrected signal to create the first corrective signal, and up-converting the filter or DAC output signal to create the second corrective signal. The transmit signal may come from an output of an RF power amplifier, and may be down-converted prior to filtering in the first filter or processing in the digital processor. The second filter may be a series filter or a shunt filter. A radio includes the circuits to perform the above method.

Abstract: A radio receiver processing path has a mixer with active interference/blocker cancellation to reduce the intensity of leaked and undesired signals by using a replica of the transmitted signal, emulating the phase and attenuation through the leakage path and subtracting the emulated signal within the mixer. Intermodulation distortions are predicted through the use of nonlinear modeling in the digital baseband between the baseband transmitter and baseband receiver and subsequently subtracted from the received signal. The nonlinear basis functions are combined to model the composite nonlinearity in the signal path based on digital baseband transmitted data. The modeled nonlinearity is subtracted from the received signal, and the result is observed and used to guide the nonlinear modeling parameters using self-contained control loops.

Abstract: In a method and apparatus for operating a super-heterodyne receiver, a tuning circuit has a local oscillator for frequency shifting a desired channel to a selected frequency and a controller for controlling the local oscillator. The controller determines for each of a number of identified channels, whether an image signal is present at frequencies in the spectrum that when tuned to a first selected frequency interfere, and is operable to select a modified selected frequency at which interference between the image signal and the identified channel is reduced.

Abstract: A receiver, such as a television tuner, includes a radio frequency (RF) filter circuit. The RF filter circuit includes a filter, a first node, and a second node coupled to the filter, and a conversion signal path having an input coupled to the first node and an output coupled to the second node, the conversion signal path having an active mixer coupled between the first node and the second node. The active mixer can include, for example, a first transconductor and a first mixer coupled in series between the first node and the second node. The RF filter circuit further includes a feedback signal path having an input coupled to the second node and an output coupled to the first node, the feedback signal path including a second transconductor and a second mixer coupled in series between the second node and the first node.

Abstract: A radio receiver processing path has a mixer with active interference/blocker cancellation to reduce the intensity of leaked and undesired signals by using a replica of the transmitted signal, emulating the phase and attenuation through the leakage path and subtracting the emulated signal within the mixer. Intermodulation distortions are predicted through the use of nonlinear modeling in the digital baseband between the baseband transmitter and baseband receiver and subsequently subtracted from the received signal. The nonlinear basis functions are combined to model the composite nonlinearity in the signal path based on digital baseband transmitted data. The modeled nonlinearity is subtracted from the received signal, and the result is observed and used to guide the nonlinear modeling parameters using self-contained control loops.

Abstract: A radio frequency (RF) receiver, such as a television tuner, includes a harmonic cancellation circuit. The harmonic cancellation circuit includes a primary signal path to generate a first intermediate frequency (IF) signal by mixing an RF signal with a reference signal and a harmonic feedforward signal path to generate a second IF signal representing signal content of the RF signal near an nth-order harmonic of a frequency fLO of the first reference signal, n comprising a positive integer. The harmonic cancellation circuit further includes a summation stage to generate a third IF signal based on a difference between the first IF signal and the second IF signal.

Abstract: A radio frequency (RF) receiver, such as a television tuner, includes a harmonic cancellation circuit. The harmonic cancellation circuit includes a primary signal path to generate a first intermediate frequency (IF) signal by mixing an RF signal with a reference signal and a harmonic feedforward signal path to generate a second IF signal representing signal content of the RF signal near an nth-order harmonic of a frequency fLO of the first reference signal, n comprising a positive integer. The harmonic cancellation circuit further includes a summation stage to generate a third IF signal based on a difference between the first IF signal and the second IF signal.

Abstract: A receiver, such as a television tuner, includes a radio frequency (RF) filter circuit. The RF filter circuit includes a filter, a first node, and a second node coupled to the filter, and a conversion signal path having an input coupled to the first node and an output coupled to the second node, the conversion signal path having an active mixer coupled between the first node and the second node. The active mixer can include, for example, a first transconductor and a first mixer coupled in series between the first node and the second node. The RF filter circuit further includes a feedback signal path having an input coupled to the second node and an output coupled to the first node, the feedback signal path including a second transconductor and a second mixer coupled in series between the second node and the first node.

Abstract: An upstream amplifier is integrated on a substrate with a digital-to-analog converter (DAC) to form an integrated circuit. In an embodiment, a low-pass filter is also integrated on the substrate. The output signal level of the upstream amplifier is controllable. In embodiments, fine adjustments are made to the output signal level of the upstream amplifier by varying a bias current of the DAC. A software control bit is used to switch between a power-on mode of operation and a power-down mode of operation. The upstream amplifier transmits in a burst mode. The power consumption of the upstream amplifier scales with the amplifier's output signal level. A high degree of matching is attained between the positive and negative paths of the upstream amplifier. This provides high immunity from common-mode disturbances such as substrate noise, clock spurs, and glitches caused by a gain change.

Abstract: An upstream amplifier is integrated on a substrate with a digital-to-analog converter (DAC) to form an integrated circuit. In an embodiment, a low-pass filter is also integrated on the substrate. The output signal level of the upstream amplifier is controllable. In embodiments, fine adjustments are made to the output signal level of the upstream amplifier by varying a bias current of the DAC. A software control bit is used to switch between a power-on mode of operation and a power-down mode of operation. The upstream amplifier transmits in a burst mode. The power consumption of the upstream amplifier scales with the amplifier's output signal level. A high degree of matching is attained between the positive and negative paths of the upstream amplifier. This provides high immunity from common-mode disturbances such as substrate noise, clock spurs, and glitches caused by a gain change.

Abstract: An upstream amplifier is integrated on a substrate with a digital-to-analog converter (DAC) to form an integrated circuit. In an embodiment, a low-pass filter is also integrated on the substrate. The output signal level of the upstream amplifier is controllable. In embodiments, fine adjustments are made to the output signal level of the upstream amplifier by varying a bias current of the DAC. A software control bit is used to switch between a power-on mode of operation and a power-down mode of operation. The upstream amplifier transmits in a burst mode. The power consumption of the upstream amplifier scales with the amplifier's output signal level. A high degree of matching is attained between the positive and negative paths of the upstream amplifier. This provides high immunity from common-mode disturbances such as substrate noise, clock spurs, and glitches caused by a gain change.

Abstract: In a method and apparatus for operating a super-heterodyne receiver, a tuning circuit has a local oscillator for frequency shifting a desired channel to a selected frequency and a controller for controlling the local oscillator. The controller determines for each of a number of identified channels, whether an image signal is present at frequencies in the spectrum that when tuned to a first selected frequency interfere, and is operable to select a modified selected frequency at which interference between the image signal and the identified channel is reduced.

Abstract: A low jitter, high phase resolution phase lock loop incorporating a ring oscillator-type VCO is designed and constructed to operate at a characteristic frequency M times higher than a required output clock frequency. Multi-phase output signals are taken from the VCO and selected through a Gray code MUX, prior to being divided down to the output clock frequency by a divide-by-M frequency divider circuit. Operating the VCO at frequencies in excess of the output clock frequency, allows jitter to be averaged across a timing cycle M and further allows a reduction in the number of output phase taps, by a scale factor M, without reducing the phase resolution or granularity of the output signal.

Abstract: An upstream amplifier is integrated on a substrate with a digital-to-analog converter (DAC) to form an integrated circuit. In an embodiment, a low-pass filter is also integrated on the substrate. The output signal level of the upstream amplifier is controllable. In embodiments, fine adjustments are made to the output signal level of the upstream amplifier by varying a bias current of the DAC. A software control bit is used to switch between a power-on mode of operation and a power-down mode of operation. The upstream amplifier transmits in a burst mode. The power consumption of the upstream amplifier scales with the amplifier's output signal level. A high degree of matching is attained between the positive and negative paths of the upstream amplifier. This provides high immunity from common-mode disturbances such as substrate noise, clock spurs, and glitches caused by a gain change.

Abstract: A low jitter, high phase resolution phase lock loop incorporating a ring oscillator-type VCO is designed and constructed to operate at a characteristic frequency M times higher than a required output clock frequency. Multi-phase output signals are taken from the VCO and selected through a Gray code MUX, prior to being divided down to the output clock frequency by a divide-by-M frequency divider circuit. Operating the VCO at frequencies in excess of the output clock frequency, allows jitter to be averaged across a timing cycle M and further allows a reduction in the number of output phase taps, by a scale factor M, without reducing the phase resolution or granularity of the output signal.

Abstract: An upstream amplifier is integrated on a substrate with a digital-to-analog converter (DAC) to form an integrated circuit. In an embodiment, a low-pass filter is also integrated on the substrate. The output signal level of the upstream amplifier is controllable. In embodiments, fine adjustments are made to the output signal level of the upstream amplifier by varying a bias current of the DAC. A software control bit is used to switch between a power-on mode of operation and a power-down mode of operation. The upstream amplifier transmits in a burst mode. The power consumption of the upstream amplifier scales with the amplifier's output signal level. A high degree of matching is attained between the positive and negative paths of the upstream amplifier. This provides high immunity from common-mode disturbances such as substrate noise, clock spurs, and glitches caused by a gain change.

Abstract: A low jitter, high phase resolution phase lock loop incorporating a ring oscillator-type VCO is designed and constructed to operate at a characteristic frequency M times higher than a required output clock frequency. Multi-phase output signals are taken from the VCO and selected through a Gray code MUX, prior to being divided down to the output clock frequency by a divide-by-M frequency divider circuit. Operating the VCO at frequencies in excess of the output clock frequency, allows jitter to be averaged across a timing cycle M and further allows a reduction in the number of output phase taps, by a scale factor M, without reducing the phase resolution or granularity of the output signal.