Abstract: An apparatus for stitching together multiple camera images to form a blended image having an output projection format. The apparatus is configured to convert each of the multiple camera images into the output projection format. It is configured to stitch together the converted images to form a single image. It is also configured to output the single image as the blended image having the output projection format.

Abstract: A data packer forma bit stream for forwarding values to memory. The bit stream includes the values and respective prefixes for identifying the values and the data packer is configured to insert the prefixes at predetermined boundaries in the bit stream, such that a prefix for identifying one value is inserted between bits that define a value identified by a preceding prefix. A data unpacker unpacks a bit stream that comprises values and respective prefixes for identifying those values that are located at predetermined boundaries in the bit stream, such that a prefix for identifying one value is inserted between bits that define a value identified by a preceding prefix. The data unpacker identifies a prefix at a predetermined boundary in the bit stream and determine, in dependence on that prefix and the predetermined boundaries, a location of the next prefix in the bit stream.

Abstract: An image processing apparatus is provided that comprises an input configured to receive an image and a Laplacian generator configured to generate, from the image, a Laplacian pyramid that represents the image as a series of frames that contain different frequency components of the image. The image processing apparatus also comprises a compressor configured to compress the Laplacian pyramid for writing to memory.

Abstract: An apparatus for filtering multiple images so that they can be stitched together to form a blended image, the apparatus comprising a plurality of filters configured such that: (i) each filter is configured to process only images from the multiple images that will be non-overlapping with each other in the blended image; and (ii) images that will overlap with each other in the blended image are processed by different filters.

Abstract: An apparatus for stitching together multiple camera images to form a blended image having an output projection format. The apparatus is configured to convert each of the multiple camera images into the output projection format. It is configured to stitch together the converted images to form a single image. It is also configured to output the single image as the blended image having the output projection format.

Abstract: A data packer is provided that is configured to form a bit stream for forwarding a plurality of values to memory. The bit stream includes the plurality of values and respective prefixes for identifying the values and the data packer is configured to insert the prefixes at predetermined boundaries in the bit stream, such that a prefix for identifying one value is inserted between bits that define a value identified by another prefix. A data unpacker is also provided that is configured to unpack a bit stream that comprises a plurality of values and respective prefixes for identifying those values that are located at predetermined boundaries in the bit stream, such that a prefix for identifying one value is inserted between bits that define a value identified by another prefix. The data unpacker is configured to identify a prefix at a predetermined boundary in the bit stream and determine, in dependence on that prefix and the predetermined boundaries, a location of the next prefix in the bit stream.

Abstract: An apparatus for combining multiple images to form a blended image, configured to identify regions of overlap: (i) in a first image and in a second image, corresponding to where those first and second images will overlap each other in the blended image; and (ii) in the first image and in a third image, corresponding to where those first and third images will overlap each other in the blended image, identify an image quality associated with each region of overlap, determine a gain for each image that, when applied to the image as a whole, will minimise a sum of: (i) a difference between the image qualities associated with the regions of overlap in the first and second images; and (ii) a difference between the image qualities associated with the regions of overlap in the first and third images and apply the respective gains to the first, second and third images.

Abstract: An image processing apparatus is provided that comprises an input configured to receive an image and a Laplacian generator configured to generate, from the image, a Laplacian pyramid that represents the image as a series of frames that contain different frequency components of the image. The image processing apparatus also comprises a compressor configured to compress the Laplacian pyramid for writing to memory.

Abstract: An apparatus for filtering multiple images so that they can be stitched together to form a blended image, the apparatus comprising a plurality of filters configured such that: (i) each filter is configured to process only images from the multiple images that will be non-overlapping with each other in the blended image; and (ii) images that will overlap with each other in the blended image are processed by different filters.

Abstract: An apparatus for combining multiple images to form a blended image, configured to identify regions of overlap: (i) in a first image and in a second image, corresponding to where those first and second images will overlap each other in the blended image; and (ii) in the first image and in a third image, corresponding to where those first and third images will overlap each other in the blended image, identify an image quality associated with each region of overlap, determine a gain for each image that, when applied to the image as a whole, will minimise a sum of: (i) a difference between the image qualities associated with the regions of overlap in the first and second images; and (ii) a difference between the image qualities associated with the regions of overlap in the first and third images and apply the respective gains to the first, second and third images.

Abstract: Roughly described, a method of restricting access of a debug controller to debug architecture on an integrated circuit chip, the debug architecture comprising an access controller, a plurality of peripheral circuits, and a shared hub, the shared hub being accessible by the access controller and the plurality of peripheral circuits, the method comprising: at the access controller, authenticating the debug controller; at the access controller, following authentication, assigning to the debug controller a set of access rights, the set of access rights granting the debug controller partial access to the debug architecture; and after assigning the set of access rights, allowing the debug controller access to the debug architecture as allowed by the set of access rights.

Abstract: Roughly described, a method of restricting access of a debug controller to debug architecture on an integrated circuit chip, the debug architecture comprising an access controller, a plurality of peripheral circuits, and a shared hub, the shared hub being accessible by the access controller and the plurality of peripheral circuits, the method comprising: at the access controller, authenticating the debug controller; at the access controller, following authentication, assigning to the debug controller a set of access rights, the set of access rights granting the debug controller partial access to the debug architecture; and after assigning the set of access rights, allowing the debug controller access to the debug architecture as allowed by the set of access rights.

Abstract: Roughly described, a method of restricting access of a debug controller to debug architecture on an integrated circuit chip, the debug architecture comprising an access controller, a plurality of peripheral circuits, and a shared hub, the shared hub being accessible by the access controller and the plurality of peripheral circuits, the method comprising: at the access controller, authenticating the debug controller; at the access controller, following authentication, assigning to the debug controller a set of access rights, the set of access rights granting the debug controller partial access to the debug architecture; and after assigning the set of access rights, allowing the debug controller access to the debug architecture as allowed by the set of access rights.

Abstract: Roughly described, a method of restricting access of a debug controller to debug architecture on an integrated circuit chip, the debug architecture comprising an access controller, a plurality of peripheral circuits, and a shared hub, the shared hub being accessible by the access controller and the plurality of peripheral circuits, the method comprising: at the access controller, authenticating the debug controller; at the access controller, following authentication, assigning to the debug controller a set of access rights, the set of access rights granting the debug controller partial access to the debug architecture; and after assigning the set of access rights, allowing the debug controller access to the debug architecture as allowed by the set of access rights.

Abstract: Roughly described, a method of restricting access of a debug controller to debug architecture on an integrated circuit chip, the debug architecture comprising an access controller, a plurality of peripheral circuits, and a shared hub, the shared hub being accessible by the access controller and the plurality of peripheral circuits, the method comprising: at the access controller, authenticating the debug controller; at the access controller, following authentication, assigning to the debug controller a set of access rights, the set of access rights granting the debug controller partial access to the debug architecture; and after assigning the set of access rights, allowing the debug controller access to the debug architecture as allowed by the set of access rights.

Abstract: A data processing apparatus having processing circuitry and debug circuitry is debugged by operating the processing circuitry to generate data. The debug circuitry is employed to generate trace elements indicative of the operation of the processing circuitry. Trace elements are caused to be output from the data processing apparatus over a communication bus capable of connecting a plurality of devices. The communication bus is controlled by a protocol for data interchange requiring data interchange from any device on the communication bus to be controlled by a single processing system. The passing of the trace elements onto the communication bus is controlled using an interface unit of the debug circuitry. The interface unit comprises a controller arranged to allow each of the interface unit and processing circuitry to be separate processing systems which can each independently control data interchange from the data processing apparatus.

Abstract: Roughly described, a method of restricting access of a debug controller to debug architecture on an integrated circuit chip, the debug architecture comprising an access controller, a plurality of peripheral circuits, and a shared hub, the shared hub being accessible by the access controller and the plurality of peripheral circuits, the method comprising: at the access controller, authenticating the debug controller; at the access controller, following authentication, assigning to the debug controller a set of access rights, the set of access rights granting the debug controller partial access to the debug architecture; and after assigning the set of access rights, allowing the debug controller access to the debug architecture as allowed by the set of access rights.

Abstract: A data processing apparatus, comprising processing circuitry, which in use, generates data and debug circuitry arranged to debug operation of the processing circuitry. The processing circuitry includes bus circuitry arranged to pass data at least one of into and out of the processing apparatus over a communication bus. The debug circuitry comprises monitoring circuitry arranged to monitor the data generated, in use, by the processing circuitry and generate a stream of trace elements. An interface unit is arranged to interface, using the bus circuitry, the trace elements generated by the monitoring circuitry onto the communication bus to be output, in use, from the processing apparatus using the communication bus. The interface unit comprises a controller which is arranged to control operation of the interface unit independently of the operation of the processing circuitry.

Abstract: A method of debugging a multiple concurrent processes comprising: obtaining, from each process, a plurality of events that have been processed and, if no time information is associated with each event, associating time information therewith; causing a display to display the events such that an event that has occurred in a first portion of the display associated with a first process at a first time is aligned with an event in a second portion of the display associated with a second process that has occurred at a similar time to the first time. To be accompanied, when published, by FIG. 5 of the drawings.

Abstract: A method of debugging a multiple concurrent processes comprising: obtaining, from each process, a plurality of events that have been processed and, if no time information is associated with each event, associating time information therewith; causing a display to display the events such that an event that has occurred in a first portion of the display associated with a first process at a first time is aligned with an event in a second portion of the display associated with a second process that has occurred at a similar time to the first time. To be accompanied, when published, by FIG. 5 of the drawings.