Patents by Inventor Stephen Joseph Schwinn
Stephen Joseph Schwinn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8291201Abstract: A pipelined execution unit incorporates one or more low power modes that reduce power consumption by dynamically merging pipeline stages in an execution pipeline together with one another. In particular, the execution logic in successive pipeline stages in an execution pipeline may be dynamically merged together by setting one or more latches that are intermediate to such pipeline stages to a transparent state such that the output of the pipeline stage preceding such latches is passed to the subsequent pipeline stage during the same clock cycle so that both such pipeline stages effectively perform steps for the same instruction during each clock cycle. Then, with the selected pipeline stages merged, the power consumption of the execution pipeline can be reduced (e.g., by reducing the clock frequency and/or operating voltage of the execution pipeline), often with minimal adverse impact on performance.Type: GrantFiled: May 22, 2008Date of Patent: October 16, 2012Assignee: International Business Machines CorporationInventors: Stephen Joseph Schwinn, Matthew Ray Tubbs, Charles David Wait
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Patent number: 8140830Abstract: A circuit arrangement and method utilize a plurality of execution units having different power and performance characteristics and capabilities within a multithreaded processor core, and selectively route instructions having different performance requirements to different execution units based upon those performance requirements. As such, instructions that have high performance requirements, such as instructions associated with primary tasks or time sensitive tasks, can be routed to a higher performance execution unit to maximize performance when executing those instructions, while instructions that have low performance requirements, such as instructions associated with background tasks or non-time sensitive tasks, can be routed to a reduced power execution unit to reduce the power consumption (and associated heat generation) associated with executing those instructions.Type: GrantFiled: May 22, 2008Date of Patent: March 20, 2012Assignee: International Business Machines CorporationInventors: Stephen Joseph Schwinn, Matthew Ray Tubbs, Charles David Wait
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Publication number: 20090293061Abstract: A circuit arrangement and method utilize a plurality of execution units having different power and performance characteristics and capabilities within a multithreaded processor core, and selectively route instructions having different performance requirements to different execution units based upon those performance requirements. As such, instructions that have high performance requirements, such as instructions associated with primary tasks or time sensitive tasks, can be routed to a higher performance execution unit to maximize performance when executing those instructions, while instructions that have low performance requirements, such as instructions associated with background tasks or non-time sensitive tasks, can be routed to a reduced power execution unit to reduce the power consumption (and associated heat generation) associated with executing those instructions.Type: ApplicationFiled: May 22, 2008Publication date: November 26, 2009Inventors: Stephen Joseph Schwinn, Matthew Ray Tubbs, Charles David Wait
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Publication number: 20090292907Abstract: A pipelined execution unit incorporates one or more low power modes that reduce power consumption by dynamically merging pipeline stages in an execution pipeline together with one another. In particular, the execution logic in successive pipeline stages in an execution pipeline may be dynamically merged together by setting one or more latches that are intermediate to such pipeline stages to a transparent state such that the output of the pipeline stage preceding such latches is passed to the subsequent pipeline stage during the same clock cycle so that both such pipeline stages effectively perform steps for the same instruction during each clock cycle. Then, with the selected pipeline stages merged, the power consumption of the execution pipeline can be reduced (e.g., by reducing the clock frequency and/or operating voltage of the execution pipeline), often with minimal adverse impact on performance.Type: ApplicationFiled: May 22, 2008Publication date: November 26, 2009Inventors: Stephen Joseph Schwinn, Matthew Ray Tubbs, Charles David Wait
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Publication number: 20090182986Abstract: A circuit arrangement and method utilize an issue rate-based predictive thermal management technique in a microprocessor or other integrated circuit that tracks the rate in which instructions are issued to one or more execution units in the processing unit, and selectively delays the issuance of subsequent instructions to the execution unit(s) based upon the tracked issue rate to predictively control the thermal output of the integrated circuit.Type: ApplicationFiled: January 16, 2008Publication date: July 16, 2009Inventors: Stephen Joseph Schwinn, Matthew Ray Tubbs, Charles David Wait
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Patent number: 7542044Abstract: An approach to optimize specular highlight generation is presented. A single microprocessor instruction is used to generate an intensity value based upon a viewing angle value. An application stores a viewing angle value in an input register. When called, the “intensity instruction” retrieves the viewing angle value from the input register, and calculates an intensity value using three distinct steps. In turn, the intensity instruction stores the intensity value in an output register for the application to retrieve and further process. In one embodiment, the invention may be implemented using PowerPC™ assembly and VMX™ or Altivec™ instructions. In this embodiment, the intensity instruction may be represented as a “vspecefp” instruction, which stands for a “vector specular estimate floating point” instruction.Type: GrantFiled: March 15, 2008Date of Patent: June 2, 2009Assignee: International Business Machines CorporationInventors: Gordon Clyde Fossum, Stephen Joseph Schwinn, Matthew Ray Tubbs
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Patent number: 7456837Abstract: A method for optimized specular highlight generation is presented. A single microprocessor instruction is used to generate an intensity value based upon a viewing angle value. An application stores a viewing angle value in an input register. When called, the “intensity instruction” retrieves the viewing angle value from the input register, and calculates an intensity value using three distinct steps. In turn, the intensity instruction stores the intensity value in an output register for the application to retrieve and further process.Type: GrantFiled: January 10, 2005Date of Patent: November 25, 2008Assignee: International Business Machines CorporationInventors: Gordon Clyde Fossum, Stephen Joseph Schwinn, Matthew Ray Tubbs
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Publication number: 20080158228Abstract: An approach to optimize specular highlight generation is presented. A single microprocessor instruction is used to generate an intensity value based upon a viewing angle value. An application stores a viewing angle value in an input register. When called, the “intensity instruction” retrieves the viewing angle value from the input register, and calculates an intensity value using three distinct steps. In turn, the intensity instruction stores the intensity value in an output register for the application to retrieve and further process. In one embodiment, the invention may be implemented using PowerPC™ assembly and VMX™ or Altivec™ instructions. In this embodiment, the intensity instruction may be represented as a “vspecefp” instruction, which stands for a “vector specular estimate floating point” instruction.Type: ApplicationFiled: March 15, 2008Publication date: July 3, 2008Inventors: Gordon Clyde Fossum, Stephen Joseph Schwinn, Matthew Ray Tubbs
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Patent number: 7143126Abstract: A method and apparatus are provided for implementing a power of two estimation function in a general purpose floating-point processor. A floating point number is stored within a memory. The floating point number includes a sign bit, a plurality of exponent bits, and a mantissa having an implied bit and a plurality of fraction bits. In response to a floating-point instruction, the mantissa is partitioned into an integer part and a fraction part, based on the exponent bits. A floating-point result is provided by assigning the integer part of the floating point number as an unbiased exponent of the floating-point result, and by utilizing combinational logic hardware for converting the fraction part of the floating point number to a fraction part of the floating point result.Type: GrantFiled: June 26, 2003Date of Patent: November 28, 2006Assignee: International Business Machines CorporationInventors: Gordon Clyde Fossum, Stephen Joseph Schwinn, Matthew Ray Tubbs
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Patent number: 6993640Abstract: A processor supports logical partitioning of hardware resources including real address spaces of a computer system. An ultra-privileged supervisor process, called a hypervisor, regulates the logical partitions and can dynamically re-allocate resources. Preferably, the processor supports hardware multithreading, each thread independently capable of being in either hypervisor, supervisor, or problem state, and is capable of entering hypervisor state only upon occurrence of certain pre-defined events. A logical partition identifier is stored in a processor register, and can be altered by the processor only when in hypervisor state. Certain bus communications contain a logical partition identifier tag, and the processor ignores such communications if the tag does not match its own logical partition identifier in its register.Type: GrantFiled: September 23, 2004Date of Patent: January 31, 2006Assignee: International Business Machines CorporationInventors: Richard William Doing, Ronald Nick Kalla, Stephen Joseph Schwinn, Edward John Silha, Kenichi Tsuchiya
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Patent number: 6883116Abstract: A method, apparatus, and computer instructions for testing hardware in a data processing system having multiple partitions. A monitor process in a first partition assigned to a first processor is initialized. A random code generation process in a second partition associated with a second processor is initialized. The random code generation process generates instructions and executes the instructions to test the second processor. The monitor process monitors the random code generation process and resets the second processor if the random code generation process fails.Type: GrantFiled: September 27, 2001Date of Patent: April 19, 2005Assignee: International Business Machines CorporationInventors: Van Hoa Lee, Charles Andrew McLaughlin, Stephen Joseph Schwinn
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Publication number: 20040267853Abstract: A method and apparatus are provided for implementing a power of two estimation function in a general purpose floating-point processor. A floating point number is stored within a memory. The floating point number includes a sign bit, a plurality of exponent bits, and a mantissa having an implied bit and a plurality of fraction bits. In response to a floating-point instruction, the mantissa is partitioned into an integer part and a fraction part, based on the exponent bits. A floating-point result is provided by assigning the integer part of the floating point number as an unbiased exponent of the floating-point result, and by utilizing combinational logic hardware for converting the fraction part of the floating point number to a fraction part of the floating point result.Type: ApplicationFiled: June 26, 2003Publication date: December 30, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION, ARMONK, NEW YORKInventors: Gordon Clyde Fossum, Stephen Joseph Schwinn, Matthew Ray Tubbs
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Patent number: 6829684Abstract: A real address range check mechanism verifies real addresses generated in a computer system which translates real addresses from effective addresses, some of the effective addresses being real addresses not requiring translation. The system has at least two operating modes. In one mode, the range checking mechanism generates an error signal responsive to detecting a real address outside a predetermined range, and in the other operating mode no error signal is generated. Preferably, the computer system's hardware resources, including real address space, is logically partitioned, partitioning being managed by an ultra-privileged process called a hypervisor. Preferably, the processor supports hardware multithreading, each thread independently capable of being in either hypervisor, supervisor, or problem state, real address range checking error signals being disabled in the hypervisor state.Type: GrantFiled: June 20, 2002Date of Patent: December 7, 2004Assignee: International Business Machines CorporationInventors: Richard William Doing, Ronald Nick Kalla, Stephen Joseph Schwinn, Edward John Silha, Kenichi Tsuchiya
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Publication number: 20030061540Abstract: A method, apparatus, and computer instructions for testing hardware in a data processing system having multiple partitions. A monitor process in a first partition assigned to a first processor is initialized. A random code generation process in a second partition associated with a second processor is initialized. The random code generation process generates instructions and executes the instructions to test the second processor. The monitor process monitors the random code generation process and resets the second processor if the random code generation process fails.Type: ApplicationFiled: September 27, 2001Publication date: March 27, 2003Applicant: International Business Machines CorporationInventors: Van Hoa Lee, Charles Andrew McLaughlin, Stephen Joseph Schwinn
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Publication number: 20030009648Abstract: A processor supports logical partitioning of hardware resources including real address spaces of a computer system. An ultra-privileged supervisor process, called a hypervisor, regulates the logical partitions and can dynamically re-allocate resources. Preferably, the processor supports hardware multithreading, each thread independently capable of being in either hypervisor, supervisor, or problem state. The processor assigns certain generated addresses to its logical partition, preferably by concatenating certain high order bits from a special register with lower order bits of the generated address. A separate range check mechanism concurrently verifies that these high order effective address bits are in fact 0, and generates an error signal if they are not.Type: ApplicationFiled: June 20, 2002Publication date: January 9, 2003Applicant: International Business Machines CorporationInventors: Richard William Doing, Ronald Nick Kalla, Stephen Joseph Schwinn, Edward John Silha, Kenichi Tsuchiya
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Patent number: 6438671Abstract: A processor supports logical partitioning of a computer system. Logical partitions isolate the real address spaces of processes executing on different processors and the hardware resources that include processors. However, this multithreaded processor system can dynamically reallocate hardware resources including the processors among logical partitions. An ultra-privileged supervisor process, called a hypervisor, regulates the logical partitions. Preferably, the processor supports hardware multithreading, each thread independently capable of being in either hypervisor, supervisor, or problem state. The processor assigns certain generated addresses to its logical partition, preferably by concatenating certain high order bits from a special register with lower order bits of the generated address. A separate range check mechanism concurrently verifies that these high order effective address bits are in fact 0, and generates an error signal if they are not.Type: GrantFiled: July 1, 1999Date of Patent: August 20, 2002Assignee: International Business Machines CorporationInventors: Richard William Doing, Ronald Nick Kalla, Stephen Joseph Schwinn, Edward John Silha, Kenichi Tsuchiya
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Patent number: 6161166Abstract: A multithreaded processor includes a level one instruction cache shared by all threads. The I-cache is accessed with an instruction unit generated effective address, the I-cache directory containing real page numbers of the corresponding cache lines. A separate line fill sequencer exists for each thread. Preferably, the I-cache is N-way set associative, where N is the number of threads, and includes an effective-to-real address table (ERAT), containing pairs of effective and real page numbers. ERAT entries are accessed by hashing the effective address. The ERAT entry is then compared with the effective address of the desired instruction to verify an ERAT hit. The corresponding real page number is compared with a real page number in the directory array to verify a cache hit. Preferably, the line fill sequencer operates in response to a cache miss, where there is an ERAT hit.Type: GrantFiled: March 10, 1999Date of Patent: December 12, 2000Assignee: International Business Machines CorporationInventors: Richard William Doing, Ronald Nick Kalla, Stephen Joseph Schwinn