Abstract: A digital test instrument and a test method provide adjustable results latency. A digital test instrument includes a pattern controller configured to generate a sequence of test patterns, responsive, at least in part, to a pass/fail result, a pattern memory configured to supply the generated sequence of test patterns to a unit under test, a pattern results collection unit configured to receive at least one result value from the unit under test and to determine a pass/fail result for at least one supplied test pattern, and a synchronization unit configured to provide a no-result indication to the pattern controller during a preset number of pattern cycles following the start of a test, the preset number of pattern cycles based on a results latency of the test instrument, and to provide pass/fail results to the pattern controller after the preset number of pattern cycles.

Abstract: A digital test instrument and a test method provide adjustable results latency. A digital test instrument includes a pattern controller configured to generate a sequence of test patterns, responsive, at least in part, to a pass/fail result, a pattern memory configured to supply the generated sequence of test patterns to a unit under test, a pattern results collection unit configured to receive at least one result value from the unit under test and to determine a pass/fail result for at least one supplied test pattern, and a synchronization unit configured to provide a no-result indication to the pattern controller during a preset number of pattern cycles following the start of a test, the preset number of pattern cycles based on a results latency of the test instrument, and to provide pass/fail results to the pattern controller after the preset number of pattern cycles.

Abstract: Protection switching of digital signal transmitting and receiving hardware is realized in a "hitless" manner. The hitless switch is obtained by employing hardware switching units which can individually determine the instant to switch from an active state to a standby state and vice versa. A switch is initialized by supplying a switch request signal from a control unit to a hardware switching unit in the active state. The active hardware switching unit, upon detecting a prescribed bit condition, for example, a predetermined bit state, of the digital signal being supplied as an output therefrom, supplies a predetermined synchronization pulse to the standby hardware switching unit. In response to the synchronization pulse, the standby hardware switching unit forces the bit condition of a bit of the digital signal to be supplied as an output therefrom resulting from a current input bit to be in the same bit condition as that detected in the active hardware unit.

Abstract: A channel bank unit for interfacing baseband user signals with a PCM carrier communications channel. The channel bank unit includes a circuit allowing verification of the transmission interity between the channel bank unit and external equipment having two-way communication with the channel bank unit. The circuit includes a first portion for evaluating the reception integrity of signals received from the external equipment and a second portion for imposing a parity sense on the signals transmitted to the external equipment that is related to the evaluation results of the first portion.