Patents by Inventor Stephen K. Mihalich

Stephen K. Mihalich has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4300061
    Abstract: A CMOS integrated circuit chip includes a conventional high voltage section and a low voltage section. An on-chip voltage regulator develops a second or pseudo substrate potential at a node that is regulated to a level that is the sum of the thresholds for NMOS and PMOS devices below the V.sub.DD potential. The low voltage section is connected between V.sub.DD and the second substrate potential node. The low voltage section is, therefore, always operated at optimum voltage regardless of device threshold voltage variations that are encountered in CMOS manufacturing. This means that even though the integrated circuit includes a low voltage section, it can be operated over the normal CMOS voltage range as if it contained only high voltage devices.
    Type: Grant
    Filed: March 15, 1979
    Date of Patent: November 10, 1981
    Assignee: National Semiconductor Corporation
    Inventors: Stephen K. Mihalich, Curtis J. Dicke
  • Patent number: 4295062
    Abstract: A CMOS Schmitt trigger circuit displays a lower trigger point that is one N channel transistor threshold above the negative power supply potential and an upper trigger point that is one P channel transistor threshold below the positive power supply potential. Thus, the circuit hysteresis loop is related to supply potential and device threshold values. When the trigger circuit is employed in a relaxation oscillator configuration, the oscillator frequency is independent of power supply voltage and manufacturing variables in the CMOS process that vary transistor threshold values.
    Type: Grant
    Filed: April 2, 1979
    Date of Patent: October 13, 1981
    Assignee: National Semiconductor Corporation
    Inventors: Stephen K. Mihalich, Thomas S. W. Wong
  • Patent number: 4240039
    Abstract: An amplifier having a differential input provides high gain, good common mode rejection, and linear response uses MOS transistors in a conventional integrated circuit construction. The circuit consists of four direct coupled stages, each one including a depletion and an enhancement transistor. The enhancement transistors are cascaded to provide a high gain common source connected amplifier. The depletion transistors in the four stages are alternately driven from the differential input terminals. This configuration provides a common mode range that can exceed the supply voltage by a wide margin. The differential response is linear and displays high gain. The common mode signal rejection is substantial. The circuit operates over a very wide range of supply voltages.
    Type: Grant
    Filed: June 11, 1979
    Date of Patent: December 16, 1980
    Assignee: National Semiconductor Corporation
    Inventor: Stephen K. Mihalich