Abstract: A bi-directional transceiver (100) having reduced circuitry and that may be formed on a non-semiconductor substrate includes impedance matching and filtering circuitry (114, 116, 122, 124, 128, 132) coupled to a non-linear diode (118) for converting a lower frequency modulated signal to a higher frequency RF transmit signal and to function as a square-law detector to envelope detect RF signals. The non-linear diode (118) includes, in one exemplary embodiment, at least two insulative layers disposed between two conductive layers, wherein a quantum well is formed between the insulators that allows only high-energy tunneling.

Abstract: A variable responsivity adaptive detector system (10) for a receiver protects a baseband amplifier from being overdriven and used to detect weak signals at the antenna (14). The RF detector system (10) includes an envelope detector (28) configured to receive an RF signal, and a power detector (20) sensing a magnitude of the received RF signal and providing a DC signal for biasing the envelope detector (28) to modify the magnitude of the received RF signal.

Abstract: A bi-directional transceiver (100) having reduced circuitry and that may be formed on a non-semiconductor substrate includes impedance matching and filtering circuitry (114, 116, 122, 124, 128, 132) coupled to a non-linear diode (118) for converting a lower frequency modulated signal to a higher frequency RF transmit signal and to function as a square-law detector to envelope detect RF signals. The non-linear diode (118) includes, in one exemplary embodiment, at least two insulative layers disposed between two conductive layers, wherein a quantum well is formed between the insulators that allows only high-energy tunneling.

Abstract: A device (10) is provided for matching the CTE between substrates (12, 14), e.g., a semiconductor substrate and packaging material. The first substrate (12) has a first coefficient of thermal expansion and the second substrate (14) has a second coefficient of thermal expansion. At least two layers (16) of liquid crystal polymer are formed between the first substrate (12) and the second substrate (14), each layer having a unique coefficient of thermal expansion progressively higher in magnitude from the first substrate (12) to the second substrate (14).

Abstract: A packaging structure (10) is provided having a hermetic sealed cavity for microelectronic applications. The packaging structure (10) comprises first and second packaging layers (12, 28) forming a cavity. Two liquid crystal polymer (LCP) layers (16, 22) are formed between and hermetically seal the first and second packaging layers (12, 28). First and second conductive strips (18, 20) are formed between the LCP layers (16, 22) and extend into the cavity. An electronic device (24) is positioned within the cavity and is coupled to the first and second conductive strips (18, 20).

Abstract: Microelectromechanical (MEMS) devices are integrated with high frequency devices on a monolithic substrate or wafer. High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. MEMS devices, such as a switch, a variable capacitance device or a temperature control structure, are formed in the base monocrystalline substrate. High frequency devices, such as transistors or diodes, are formed in the overlaying layer of monocrystalline materials.

Abstract: Controlling and controlled components are integrated on a monolithic device. High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.