Abstract: The present disclosure relates generally to a roofing system including flashing, for example, suitable for protecting a roof from water leakage. The present disclosure relates more particularly to a roofing system including first, second, and third courses of shingles, where the second course overlaps the first and the third course overlaps the second. A flashing plate is disposed over the first course of shingles and partially under the second course of shingles. The flashing plate and the third course of shingles are spaced apart by a gap in a direction of the slope of the roof between a top edge of the flashing plate and a lower edge of the third course of shingles.

Abstract: A Foundational Framework (“the Framework”) may refer to an apparatus that connects a multiplicity of potentially very complex components, each of which produce different types of information related to financial forecast, while maintaining a distributed and federated model to allow high autonomy to each component. The innovative Framework provides a unified operation of lifecycle of every component and allows the production of unlimited types of forecasts of different dimensions and for different purposes using a common tool that is responsible of coordinating and running the sequence of components for the user's needs.

Abstract: The present disclosure relates generally to a roofing system including flashing, for example, suitable for protecting a roof from water leakage. The present disclosure relates more particularly to a roofing system including first, second, and third courses of shingles, where the second course overlaps the first and the third course overlaps the second. A flashing plate is disposed over the first course of shingles and partially under the second course of shingles. The flashing plate and the third course of shingles are spaced apart by a gap in a direction of the slope of the roof between a top edge of the flashing plate and a lower edge of the third course of shingles.

Abstract: The present disclosure relates generally to a roofing system including flashing, for example, suitable for protecting a roof from water leakage. The present disclosure relates more particularly to a roofing system including first, second, and third courses of shingles, where the second course overlaps the first and the third course overlaps the second. A flashing plate is disposed over the first course of shingles and partially under the second course of shingles. The flashing plate and the third course of shingles are spaced apart by a gap in a direction of the slope of the roof between a top edge of the flashing plate and a lower edge of the third course of shingles.

Abstract: A method for decision tree-based management of market risk stress scenarios may include: receiving, from a front office system, a shock request comprising a scenario and a risk factor; retrieving the scenario from a scenario definition store, the scenario definition store comprising a plurality of scenarios; normalizing the risk factor resulting in standardized risk exposure; retrieving, from the retrieved scenario, a decision tree matching a risk factor type for the standardized risk factor, the decision tree comprising a plurality of nodes, each node having a shock instruction comprising an explicit shock instruction or no shock instruction; traversing the decision tree to identify a node that matches the standardized risk factor; and returning the shock instruction to the front office system, the returned shock instruction comprising the explicit shock instruction associated with the matching node or the last explicit shock instruction traversed before traversing to the matching node.

Abstract: The present disclosure relates generally to a roofing system including flashing, for example, suitable for protecting a roof from water leakage. The present disclosure relates more particularly to a roofing system including first, second, and third courses of shingles, where the second course overlaps the first and the third course overlaps the second. A flashing plate is disposed over the first course of shingles and partially under the second course of shingles. The flashing plate and the third course of shingles are spaced apart by a gap in a direction of the slope of the roof between a top edge of the flashing plate and a lower edge of the third course of shingles.

Abstract: A Foundational Framework (“the Framework”) may refer to an apparatus that connects a multiplicity of potentially very complex components, each of which produce different types of information related to financial forecast, while maintaining a distributed and federated model to allow high autonomy to each component. The innovative Framework provides a unified operation of lifecycle of every component and allows the production of unlimited types of forecasts of different dimensions and for different purposes using a common tool that is responsible of coordinating and running the sequence of components for the user's needs.

Abstract: A computer-implemented method for analyzing supply chain sensitivity based on a supply chain model is described. The method comprises defining a plurality of input parameters and an objective for the supply chain model Each of the input parameters includes a plurality of values within a respective range. The method further comprises obtaining a plurality of configurations of the supply chain for achieving the objective by applying the values of the input parameters to the supply chain model and generating a graphical representation for the objective based on the configurations of the supply chain. The graphical representation includes a plurality of data points, each of the data points representing a configuration of the supply chain.

Abstract: A method, an apparatus, and a computer program are provided to utilize built-in self test (BIST) latches for multiple purposes. Conventionally, BIST latches are single purpose. Hence, separate latches are utilized for array built-in self test (ABIST) and logic built-in self test (LBIST) operations. By having the separate latches, though, a substantial amount area is lost. Therefore, to better utilize the latches and the area, ABIST latches are reconfigured to utilize some previously unused ports to allow for multiple uses for the latches, such as for LBIST.

Abstract: A method is provided to utilize built-in self test (BIST) latches for multiple purposes. Conventionally, BIST latches are single purpose. Hence, separate latches are utilized for array built-in self test (ABIST) and logic built-in self test (LBIST) operations. By having the separate latches, though, a substantial amount area is lost. Therefore, to better utilize the latches and the area, ABIST latches are reconfigured to utilize some previously unused ports to allow for multiple uses for the latches, such as for LBIST.

Abstract: A method, an apparatus, and a computer program are provided to utilize built-in self test (BIST) latches for multiple purposes. Conventionally, BIST latches are single purpose. Hence, separate latches are utilized for array built-in self test (ABIST) and logic built-in self test (LBIST) operations. By having the separate latches, though, a substantial amount area is lost. Therefore, to better utilize the latches and the area, ABIST latches are reconfigured to utilize some previously unused ports to allow for multiple uses for the latches, such as for LBIST.

Abstract: A hip, ridge or rake shingle comprised of a plurality of panels sandwiched on each panel portion side of a layer of shingle material, such that each panel portion can be folded along a fold line, and wherein tabs are provided for each panel portion, adapted to be bent backwardly upon themselves, sandwiching thickening panels therebetween. The shingles can be laid up on a hip, ridge or rake of a roof, to yield desirable thickened features.

Abstract: A shingle and a method of making it is provided in which the rear surface of the shingle is provided with an attached reinforcement layer through which fasteners may be applied when the shingle is applied to a roof.

Abstract: A method and apparatus are provided in an array built in self test (ABIST) environment formed on a semiconductor chip having an array of memory cells arranged in columns and rows and column and row redundant lines which includes testing the array along the columns to identify a given number of faulty cells in each of the columns, storing the column addresses having the given number of faulty cells in first registers, further testing the array along the columns or rows to identify any additional faulty cells while masking the cells having the stored column addresses and storing the row addresses having the faulty cell in second registers until all of the second registers store row addresses, and after all of the second registers store row addresses, continue testing the array while masking the cells having the stored column or row addresses and storing the column addresses of any remaining additional faulty cell in any unused register of the first registers.

Abstract: An Array Built-In Self Test (ABIST) circuit places on-chip circuits such as memory arrays in a known state, then stops. In the alternative, the ABIST circuit may initialize to a particular subcycle within a pattern sequence, and repeatedly loop on the subcycle, or repeatedly loop on the entire pattern sequence.

Abstract: A method and apparatus are provided in an array built in self test (ABIST) environment formed on a semiconductor chip having an array of memory cells arranged in columns and rows and column and row redundant lines which includes testing the array along the columns to identify a given number of faulty cells in each of the columns, storing the column addresses having the given number of faulty cells in first registers, further testing the array along the columns or rows to identify any additional faulty cells while masking the cells having the stored column addresses and storing the row addresses having the faulty cell in second registers until all of the second registers store row addresses, and after all of the second registers store row addresses, continue testing the array while masking the cells having the stored column or row addresses and storing the column addresses of any remaining additional faulty cell in any unused register of the first registers.

Abstract: An ABIST circuit for testing a memory array has a blanket write subcycle (WC), an RC3 subcycle, and an RC4 subcycle. The ABIST circuit includes a programmable pattern generator that provides eight programmable data bits, eight programmable read/write bits, and two programmable address frequency bits to determine the specific test patterns applied to the memory array. The address frequency bits determine how many memory cycles will be performed on each cell of the memory array. In X1 mode, only one memory cycle is performed on each cell during any given subcycle. In X2 mode, two memory cycles are performed on each cell, allowing a cell to be written, then subsequently read in the same subcycle. In X4 mode, four memory cycles are performed on each cell, and in X8 mode, all eight bits of read/write and data are used on each cell, resulting in eight memory cycles for each cell within the memory array.

Abstract: The present invention provides a device for testing memory having write cycles and read cycles. A BIST state machine changes the data applied to the memory's DI port during read cycles to a value different from that of the data stored in the currently addressed memory location. The BIST-generated expect data also is at a different value from that of data at the memory's DI port and at the same value as the data stored at the current memory address location during read operations. With this arrangement, flush through defects can be detected which would not have been detectable by prior BIST machines.

Abstract: An ABIST circuit for testing a memory array has a blanket write subcycle (WC), an RC.sub.3 subcycle, and an RC.sub.4 subcycle. The ABIST circuit includes a programmable pattern generator that provides eight programmable data bits, eight programmable read/write bits, and two programmable address frequency bits to determine the specific test patterns applied to the memory array. The address frequency bits determine how many memory cycles will be performed on each cell of the memory array. In X1 mode, only one memory cycle is performed on each cell during any given subcycle. In X2 mode, two memory cycles are performed on each cell, allowing a cell to be written, then subsequently read in the same subcycle, In X4 mode, four memory cycles are performed on each cell, and in Xg mode, all eight bits of read/write and data are used on each cell, resulting in eight memory cycles for each cell within the memory array.

Abstract: A method and circuit are provided to detect if any bit stored in a given location in a memory is different from the data expected. The circuit includes logic to read each of the bits stored in the cells at given locations from memory and to generate a fail signal based on the data expected to be stored if the stored data is different from the expected data. The circuit also preferably includes logic to compare the True data and expect data read from each cell and generating the fail signal if they are the same. Additional logic circuitry is also preferably provided which determines if a node of the circuit remains in a precharged condition.