Abstract: A multi-die semiconductor package includes a first integrated circuit (IC) die having a first intrinsic performance level and a second IC die having a second intrinsic performance level different from the first intrinsic performance level. A power management controller distributes, based on a determined die performance differential between the first IC die and the second IC die, a level of power allocated to the semiconductor chip package between the first IC die and the second IC die. In this manner, the first IC die receives and operates at a first level of power resulting in performance exceeding its intrinsic performance level. The second IC die receives and operates at a second level of power resulting in performance below its intrinsic performance level, thereby reducing performance differentials between the IC dies.

Abstract: An apparatus and method for efficiently updating power supply voltages due to degradation from aging. A computing system includes one or more functional units and a runtime voltage calibrator (or calibrator). The calibrator is capable of performing power supply calibration for the one or more supply voltage power rail used by the one or more functional units. The calibrator identifies a particular ground reference power rail that is received by the one or more functional units. The calibrator also identifies a first supply voltage power rail that is received by at least a first functional unit of the one or more functional units. If the runtime voltage calibrator determines that all circuitry that uses the particular ground reference power rail is idle, the calibrator performs power supply calibration for the first supply voltage power rail. The calibrator does not wait for a bootup operation and avoids interference from ground bounce.

Abstract: A multi-die semiconductor package includes a first integrated circuit (IC) die having a first intrinsic performance level and a second IC die having a second intrinsic performance level different from the first intrinsic performance level. A power management controller distributes, based on a determined die performance differential between the first IC die and the second IC die, a level of power allocated to the semiconductor chip package between the first IC die and the second IC die. In this manner, the first IC die receives and operates at a first level of power resulting in performance exceeding its intrinsic performance level. The second IC die receives and operates at a second level of power resulting in performance below its intrinsic performance level, thereby reducing performance differentials between the IC dies.

Abstract: One or more components of a computing device are run by default in a boost mode state. The one or more components continue to run in the boost mode state until the boost mode state is no longer sustainable, e.g., due to power consumption of the one or more components or temperature of the one or more components. The one or more components are switched to a reduced power state (e.g., a non-boost mode state) in response to the boost mode state no longer being sustainable. When operating the one or more components in the boost mode state again becomes sustainable due to power consumption or temperature of the one or more components, the one or more components are returned to the default boost mode state.

Abstract: A processing system adjusts an operating state of one or more processors during execution of a workload based on a command paired with the workload. The command specifies a desired operating state or a performance or power efficiency target operational goal and is enqueued asynchronously with the workload. A power management controller reads the command synchronously with dispatching the workload to the processor. By asynchronously enqueuing the tag with the workload, the processing system tunes the operating state of the processor to reach higher performance, higher performance per watt, and/or higher energy efficiency during processing of the workload.

Abstract: A method for reducing power variations resulting from changes in processor workload includes communicating a power dip condition to a workload scheduler of a processor device in response to identifying the power dip condition. One or more target power workloads are assigned for execution at the processor device based at least in part on the power dip condition. Further, each of the one or more target power workloads is associated with a known power load.

Abstract: A multi-die semiconductor package includes a first integrated circuit (IC) die having a first intrinsic performance level and a second IC die having a second intrinsic performance level different from the first intrinsic performance level. A power management controller distributes, based on a determined die performance differential between the first IC die and the second IC die, a level of power allocated to the semiconductor chip package between the first IC die and the second IC die. In this manner, the first IC die receives and operates at a first level of power resulting in performance exceeding its intrinsic performance level. The second IC die receives and operates at a second level of power resulting in performance below its intrinsic performance level, thereby reducing performance differentials between the IC dies.