Patents by Inventor Stephen L. Blinick
Stephen L. Blinick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10331568Abstract: Provided are a computer program product, system, and method for locking a cache line for a burst write operations on a bus. A cache line is allocated in a cache for a target address. A lock is set for the cache line, wherein setting the lock prevents the data in the cache line from being cast out. Data is written to the cache line. All the data in the cache line is flushed to the target address over a bus in response to completing writing to the cache line.Type: GrantFiled: May 25, 2018Date of Patent: June 25, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen L. Blinick, Charles S. Cardinell, Roger G. Hathorn, Benhard Laubli, Miguel A. Montoya, Timothy J. Van Patten
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Patent number: 10152423Abstract: The population of data to be admitted into secondary data storage cache of a data storage system is controlled by determining heat metrics of data of the data storage system. If candidate data is submitted for admission into the secondary cache, data is selected to tentatively be evicted from the secondary cache; candidate data provided to the secondary data storage cache is rejected if its heat metric is less than the heat metric of the tentatively evicted data; and candidate data submitted for admission to the secondary data storage cache is admitted if its heat metric is equal to or greater than the heat metric of the tentatively evicted data.Type: GrantFiled: October 31, 2011Date of Patent: December 11, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin J. Ash, Michael T. Benhase, Stephen L. Blinick, Evangelos S. Eleftheriou, Lokesh M. Gupta, Robert Haas, Xiao-Yu Hu, Ioannis Koltsidas, Roman A. Pletka
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Publication number: 20180276133Abstract: Provided are a computer program product, system, and method for locking a cache line for a burst write operations on a bus. A cache line is allocated in a cache for a target address. A lock is set for the cache line, wherein setting the lock prevents the data in the cache line from being cast out. Data is written to the cache line. All the data in the cache line is flushed to the target address over a bus in response to completing writing to the cache line.Type: ApplicationFiled: May 25, 2018Publication date: September 27, 2018Applicants: International Business Machines Corporation, International Business Machines CorporationInventors: Stephen L. Blinick, Charles S. Cardinell, Roger G. Hathorn, Benhard Laubli, Miguel A. Montoya, Timothy J. Van Patten
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Patent number: 10049050Abstract: Provided are a computer program product, system, and method for locking a cache line for a burst write operations on a bus. A cache line is allocated in a cache for a target address. A lock is set for the cache line, wherein setting the lock prevents the data in the cache line from being cast out. Data is written to the cache line. All the data in the cache line is flushed to the target address over a bus in response to completing writing to the cache line.Type: GrantFiled: July 25, 2016Date of Patent: August 14, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen L. Blinick, Charles S. Cardinell, Roger G. Hathorn, Bernhard Laubli, Miguel A. Montoya, Timothy J. Van Patten
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Publication number: 20160335189Abstract: Provided are a computer program product, system, and method for locking a cache line for a burst write operations on a bus. A cache line is allocated in a cache for a target address. A lock is set for the cache line, wherein setting the lock prevents the data in the cache line from being cast out. Data is written to the cache line. All the data in the cache line is flushed to the target address over a bus in response to completing writing to the cache line.Type: ApplicationFiled: July 25, 2016Publication date: November 17, 2016Inventors: Stephen L. Blinick, Charles S. Cardinell, Roger G. Hathorn, Benhard Laubli, Miguel A. Montoya, Timothy J. Van Patten
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Patent number: 9436607Abstract: Provided are a computer program product, system, and method for locking a cache line for a burst write operations on a bus. A cache line is allocated in a cache for a target address. A lock is set for the cache line, wherein setting the lock prevents the data in the cache line from being cast out. Data is written to the cache line. All the data in the cache line is flushed to the target address over a bus in response to completing writing to the cache line.Type: GrantFiled: May 14, 2015Date of Patent: September 6, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen L. Blinick, Charles S. Cardinell, Roger G. Hathorn, Bernhard Laubli, Miguel A. Montoya, Timothy J. Van Patten
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Patent number: 9417808Abstract: For efficient track destage in secondary storage in a more effective manner, for temporal bits employed with sequential bits for controlling the timing for destaging the track in a primary storage, if a first bit has at least one of a lower amount of holes and a hotter data heat metric, it is moved to the lower speed cache level. If the first bit has a hotter data heat and greater than a predetermined number of holes, the first bit is discarded.Type: GrantFiled: September 25, 2015Date of Patent: August 16, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael T. Benhase, Stephen L. Blinick, Evangelos S. Eleftheriou, Lokesh M. Gupta, Robert Haas, Xiao-Yu Hu, Matthew J. Kalos, Ioannis Koltsidas, Karl A. Nielsen, Roman A. Pletka
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Publication number: 20160188478Abstract: A computer program product, system, and method for managing metadata for caching devices during shutdown and restart procedures. Fragment metadata for each fragment of data from the storage server stored in the cache device is generated. The fragment metadata is written to at least one chunk of storage in the cache device in a metadata directory in the cache device. For each of the at least one chunk in the cache device to which the fragment metadata is written, chunk metadata is generated for the chunk and writing the generated chunk metadata to the metadata directory in the cache device. Header metadata having information on access of the storage server is written to the metadata directory in the cache device. The written header metadata, chunk metadata, and fragment metadata are used to validate the metadata directory and the fragment data in the cache device during a restart operation.Type: ApplicationFiled: June 25, 2015Publication date: June 30, 2016Inventors: Stephen L. Blinick, Clement L. Dickey, Xioa-Yu Hu, Nikolas Ioannou, Ioannis Koltsidas, Paul H. Muench, Roman Pletka, Sangeetha Seshadri
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Patent number: 9372702Abstract: Updating code of a single processor in a multi-processor system includes commencing of a self-reset of a first processor if a bit is found in a first state, and interrupts associated with the first processor are disabled. Only those system resources exclusively associated with the first processor are reset, and memory transactions associated with the first processor are disabled. An image of the new code is copied into memory associated with the first processor, registers associated with the first processor are reset and the new code is booted by the first processor.Type: GrantFiled: November 25, 2014Date of Patent: June 21, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen L. Blinick, Chiahong Chen
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Patent number: 9274975Abstract: For movement of partial data segments within a computing storage environment having lower and higher levels of cache by a processor, a whole data segment containing one of the partial data segments is promoted to both the lower and higher levels of cache, including considering an Input/Output Performance (IOP) metric, a bandwidth metric, and a garbage collection metric, and a whole data segment is promoted containing the one of the partial data segments to both the lower and higher levels of cache.Type: GrantFiled: June 22, 2015Date of Patent: March 1, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael T. Benhase, Stephen L. Blinick, Evangelos S. Eleftheriou, Lokesh M. Gupta, Robert Haas, Xiao-Yu Hu, Matthew J. Kalos, Ioannis Koltsidas, Roman A. Pletka
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Publication number: 20160019000Abstract: For efficient track destage in secondary storage in a more effective manner, for temporal bits employed with sequential bits for controlling the timing for destaging the track in a primary storage, if a first bit has at least one of a lower amount of holes and a hotter data heat metric, it is moved to the lower speed cache level. If the first bit has a hotter data heat and greater than a predetermined number of holes, the first bit is discarded.Type: ApplicationFiled: September 25, 2015Publication date: January 21, 2016Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael T. BENHASE, Stephen L. BLINICK, Evangelos S. ELEFTHERIOU, Lokesh M. GUPTA, Robert HAAS, Xiao-Yu HU, Matthew J. KALOS, Ioannis KOLTSIDAS, Karl A. NIELSEN, Roman A. PLETKA
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Patent number: 9208094Abstract: Systems and methods are provided for managing storage cache resources among all servers within the cluster storage environment. A method includes partitioning a main cache of a corresponding node into a global cache and a local cache, sharing each global cache of each node with other ones of the nodes of the multiple nodes, and dynamically adjusting a ratio of an amount of space of the main cache making up the global cache and an amount of space of the main cache making up the local cache, based on access latency and cache hit over a predetermined period of time of each of the global cache and the local cache.Type: GrantFiled: August 6, 2013Date of Patent: December 8, 2015Assignee: GlobalFoudries, Inc.Inventors: Stephen L. Blinick, Daniel W. Fok, Chao G. Li, Yang Liu, Paul H. Muench
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Patent number: 9176884Abstract: For efficient track destage in secondary storage in a more effective manner, for temporal bits employed with sequential bits for controlling the timing for destaging the track in a primary storage, a preference of movement to lower speed cache level is implemented based on at least one of an amount of holes and a data heat metric. If a first bit has at least one of a lower amount of holes and a hotter data heat metric, it is moved to the lower speed cache level ahead of a second bit that has at least one of a higher amount of holes and a cooler data heat. If the first bit has a hotter data heat and greater than a predetermined number of holes, the first bit is discarded.Type: GrantFiled: December 10, 2014Date of Patent: November 3, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael T. Benhase, Stephen L. Blinick, Evangelos S. Eleftheriou, Lokesh M. Gupta, Robert Haas, Xiao-Yu Hu, Matthew J. Kalos, Ioannis Koltsidas, Karl A. Nielsen, Roman A. Pletka
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Publication number: 20150286580Abstract: For movement of partial data segments within a computing storage environment having lower and higher levels of cache by a processor, a whole data segment containing one of the partial data segments is promoted to both the lower and higher levels of cache, including considering an Input/Output Performance (IOP) metric, a bandwidth metric, and a garbage collection metric, and a whole data segment is promoted containing the one of the partial data segments to both the lower and higher levels of cache.Type: ApplicationFiled: June 22, 2015Publication date: October 8, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael T. BENHASE, Stephen L. BLINICK, Evangelos S. ELEFTHERIOU, Lokesh M. GUPTA, Robert HAAS, Xiao-Yu HU, Matthew J. KALOS, Ioannis KOLTSIDAS, Roman A. PLETKA
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Patent number: 9152599Abstract: A method for managing cache memories includes providing a computerized system including a shared data storage system (CS) configured to interact with several local servers that serve applications using respective cache memories, and access data stored in the shared data storage system; providing cache data information from each of the local servers to the shared data storage system, the cache data information comprising cache hit data representative of cache hits of each of the local servers, and cache miss data representative of cache misses of each of the local servers; aggregating, at the shared data storage system, at least part of the cache hit and miss data received and providing the aggregated cache data information to one or more of the local servers; and at the local servers, updating respective one or more cache memories used to serve respective one or more applications based on the aggregated cache data information.Type: GrantFiled: June 18, 2013Date of Patent: October 6, 2015Assignee: International Business Machines CorporationInventors: Stephen L. Blinick, Lawrence Y. Chiu, Evangelos S. Eleftheriou, Robert Haas, Yu-Cheng Hsu, Xiao-Yu Hu, Ioannis Koltsidas, Paul H. Muench, Roman Pletka
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Publication number: 20150248351Abstract: Provided are a computer program product, system, and method for locking a cache line for a burst write operations on a bus. A cache line is allocated in a cache for a target address. A lock is set for the cache line, wherein setting the lock prevents the data in the cache line from being cast out. Data is written to the cache line. All the data in the cache line is flushed to the target address over a bus in response to completing writing to the cache line.Type: ApplicationFiled: May 14, 2015Publication date: September 3, 2015Inventors: Stephen L. Blinick, Charles S. Cardinell, Roger G. Hathorn, Benhard Laubli, Miguel A. Montoya, Timothy J. Van Patten
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Patent number: 9086979Abstract: For movement of partial data segments within a computing storage environment having lower and higher levels of cache by a processor, a whole data segment containing one of the partial data segments is promoted to both the lower and higher levels of cache. Requested data of the whole data segment is split and positioned at a Most Recently Used (MRU) portion of a demotion queue of the higher level of cache.Type: GrantFiled: March 18, 2014Date of Patent: July 21, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael T. Benhase, Stephen L. Blinick, Evangelos S. Eleftheriou, Lokesh M. Gupta, Robert Haas, Xiao-Yu Hu, Matthew J. Kalos, Ioannis Koltsidas, Roman A. Pletka
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Patent number: 9086972Abstract: A computer program product, system, and method for managing metadata for caching devices during shutdown and restart procedures. Fragment metadata for each fragment of data from the storage server stored in the cache device is generated. The fragment metadata is written to at least one chunk of storage in the cache device in a metadata directory in the cache device. For each of the at least one chunk in the cache device to which the fragment metadata is written, chunk metadata is generated for the chunk and writing the generated chunk metadata to the metadata directory in the cache device. Header metadata having information on access of the storage server is written to the metadata directory in the cache device. The written header metadata, chunk metadata, and fragment metadata are used to validate the metadata directory and the fragment data in the cache device during a restart operation.Type: GrantFiled: July 8, 2013Date of Patent: July 21, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen L. Blinick, Clement L. Dickey, Xioa-Yu Hu, Nikolas Ioannou, Ioannis Koltsidas, Paul H. Muench, Roman Pletka, Sangeetha Seshadri
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Patent number: 9075720Abstract: Provided are a computer program product, system, and method for locking a cache line for a burst write operations on a bus. A cache line is allocated in a cache for a target address. A lock is set for the cache line, wherein setting the lock prevents the data in the cache line from being cast out. Data is written to the cache line. All the data in the cache line is flushed to the target address over a bus in response to completing writing to the cache line.Type: GrantFiled: October 4, 2010Date of Patent: July 7, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen L. Blinick, Charles S. Cardinell, Roger G. Hathorn, Bernhard Laubli, Miguel A. Montoya, Timothy J. Van Patten
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Publication number: 20150100776Abstract: Updating code of a single processor in a multi-processor system includes commencing of a self-reset of a first processor if a bit is found in a first state, and interrupts associated with the first processor are disabled. Only those system resources exclusively associated with the first processor are reset, and memory transactions associated with the first processor are disabled. An image of the new code is copied into memory associated with the first processor, registers associated with the first processor are reset and the new code is booted by the first processor.Type: ApplicationFiled: November 25, 2014Publication date: April 9, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen L. BLINICK, Chiahong CHEN