Abstract: A multi-channel current pulse generator for driving a plurality of loads with unique positive terminals and a shared negative terminal. The pulse generator comprises a pulse control transistor and, for each load, a load capacitor and a charging control transistor. The pulse control transistor allows or blocks current pulses through the loads and has a drain terminal connected to the shared negative terminal, a source terminal connected to ground, and a gate terminal for receiving a load driver control signal. The load capacitors are discharged by current pulses through the corresponding loads. The charging control transistors allow or block charging currents for the corresponding load capacitors. The pulse control transistor is preferably an enhancement mode GaN FET and is chosen to withstand current pulses through a maximum number of loads to be driven simultaneously.

Abstract: A current pulse generator circuit configured to be monolithically integrated into a single semiconductor die and provide high pulsing frequencies. A first GaN FET transistor controls the charging of a capacitor in a boost converter. A second GaN FET transistor controls the discharging of the capacitor through a load, such as a laser diode, connected to the boost converter. Both GaN FET transistors are preferably enhancement mode GaN FETs and may be integrated into the single semiconductor die, together with gate drivers. The diode in a conventional boost converter circuit can also be implemented in the present invention as a GaN FET transistor, and also integrated into the single semiconductor die.

Abstract: A circuit for providing an adjustable output driver current for use in LiDAR or other similar GaN driver applications. The circuit creates an appropriate gate-to-source voltage, VGS, for a high-current GaN driver FET to obtain a desired, high slew-rate driver current, IDRV. An externally provided reference current is used to create the required VGS for the driver FET, which is stored on an external capacitor. The value of the capacitor far exceeds the relatively low input-capacitance of the GaN driver FET. When a pulse IDRV of desired value is needed, the voltage on the capacitor is impinged upon the gate of the driver FET, thereby creating the desired IDRV. The reference charging circuit replenishes any charge lost on the capacitor, so that the same desired IDRV can be obtained on the next command pulse.

Abstract: A multi-channel current pulse generator for driving a plurality of loads with unique positive terminals and a shared negative terminal. The pulse generator comprises a pulse control transistor and, for each load, a load capacitor and a charging control transistor. The pulse control transistor allows or blocks current pulses through the loads and has a drain terminal connected to the shared negative terminal, a source terminal connected to ground, and a gate terminal for receiving a load driver control signal. The load capacitors are discharged by current pulses through the corresponding loads. The charging control transistors allow or block charging currents for the corresponding load capacitors. The pulse control transistor is preferably an enhancement mode GaN FET and is chosen to withstand current pulses through a maximum number of loads to be driven simultaneously.

Abstract: A circuit for providing an adjustable output driver current for use in LiDAR or other similar GaN driver applications. The circuit creates an appropriate gate-to-source voltage, VGS, for a high-current GaN driver FET to obtain a desired, high slew-rate driver current, IDRV. An externally provided reference current is used to create the required VGS for the driver FET, which is stored on an external capacitor. The value of the capacitor far exceeds the relatively low input-capacitance of the GaN driver FET. When a pulse IDRV of desired value is needed, the voltage on the capacitor is impinged upon the gate of the driver FET, thereby creating the desired IDRV. The reference charging circuit replenishes any charge lost on the capacitor, so that the same desired IDRV can be obtained on the next command pulse.

Abstract: A current pulse generator circuit configured to be monolithically integrated into a single semiconductor die and provide high pulsing frequencies. A first GaN FET transistor controls the charging of a capacitor in a boost converter. A second GaN FET transistor controls the discharging of the capacitor through a load, such as a laser diode, connected to the boost converter. Both GaN FET transistors are preferably enhancement mode GaN FETs and may be integrated into the single semiconductor die, together with gate drivers. The diode in a conventional boost converter circuit can also be implemented in the present invention as a GaN FET transistor, and also integrated into the single semiconductor die.

Abstract: A GaN transistor with reduced output capacitance and a method form manufacturing the same. The GaN transistor device includes a substrate layer, one or more buffer layer disposed on a substrate layer, a barrier layer disposed on the buffer layers, and a two dimensional electron gas (2DEG) formed at an interface between the barrier layer and the buffer layer. Furthermore, a gate electrode is disposed on the barrier layer and a dielectric layer is disposed on the gate electrode and the barrier layer. The GaN transistor includes one or more isolation regions formed in a portion of the interface between the at least one buffer layer and the barrier layer to remove the 2DEG in order to reduce output capacitance Coss of the GaN transistor.

Abstract: A semiconductor device includes a semiconductor substrate, a first p-channel laterally diffused metal oxide semiconductor (LDMOS) transistor formed over the semiconductor substrate and additional p-channel LDMOS transistors formed over the semiconductor substrate. First drain and gate electrodes are formed over the substrate and are coupled to the first LDMOS transistor. Additional drain and gate electrodes are formed over the substrate and are coupled to the second LDMOS transistor. A common source electrode for the first and second LDMOS transistors is also formed over the substrate.

Abstract: A GaN transistor with reduced output capacitance and a method form manufacturing the same. The GaN transistor device includes a substrate layer, one or more buffer layer disposed on a substrate layer, a barrier layer disposed on the buffer layers, and a two dimensional electron gas (2DEG) formed at an interface between the barrier layer and the buffer layer. Furthermore, a gate electrode is disposed on the barrier layer and a dielectric layer is disposed on the gate electrode and the barrier layer. The GaN transistor includes one or more isolation regions formed in a portion of the interface between the at least one buffer layer and the barrier layer to remove the 2DEG in order to reduce output capacitance Coss of the GaN transistor.

Abstract: A semiconductor device includes a semiconductor substrate, a first p-channel laterally diffused metal oxide semiconductor (LDMOS) transistor formed over the semiconductor substrate and additional p-channel LDMOS transistors formed over the semiconductor substrate. First drain and gate electrodes are formed over the substrate and are coupled to the first LDMOS transistor. Additional drain and gate electrodes are formed over the substrate and are coupled to the second LDMOS transistor. A common source electrode for the first and second LDMOS transistors is also formed over the substrate.

Abstract: A semiconductor device includes a semiconductor substrate, a first p-channel laterally diffused metal oxide semiconductor (LDMOS) transistor formed over the semiconductor substrate and additional p-channel LDMOS transistors formed over the semiconductor substrate. First drain and gate electrodes are formed over the substrate and are coupled to the first LDMOS transistor. Additional drain and gate electrodes are formed over the substrate and are coupled to the second LDMOS transistor. A common source electrode for the first and second LDMOS transistors is also formed over the substrate.

Abstract: A semiconductor device includes a semiconductor substrate, a first p-channel laterally diffused metal oxide semiconductor (LDMOS) transistor formed over the semiconductor substrate and additional p-channel LDMOS transistors formed over the semiconductor substrate. First drain and gate electrodes are formed over the substrate and are coupled to the first LDMOS transistor. Additional drain and gate electrodes are formed over the substrate and are coupled to the second LDMOS transistor. A common source electrode for the first and second LDMOS transistors is also formed over the substrate.

Abstract: A semiconductor device includes a semiconductor substrate, a first p-channel laterally diffused metal oxide semiconductor (LDMOS) transistor formed over the semiconductor substrate and additional p-channel LDMOS transistors formed over the semiconductor substrate. First drain and gate electrodes are formed over the substrate and are coupled to the first LDMOS transistor. Additional drain and gate electrodes are formed over the substrate and are coupled to the second LDMOS transistor. A common source electrode for the first and second LDMOS transistors is also formed over the substrate.

Abstract: A semiconductor device includes a semiconductor substrate, a first p-channel laterally diffused metal oxide semiconductor (LDMOS) transistor formed over the semiconductor substrate and additional p-channel LDMOS transistors formed over the semiconductor substrate. First drain and gate electrodes are formed over the substrate and are coupled to the first LDMOS transistor. Additional drain and gate electrodes are formed over the substrate and are coupled to the second LDMOS transistor. A common source electrode for the first and second LDMOS transistors is also formed over the substrate.