Abstract: Embodiments of a scannable IO circuit featuring reduced latch count for pipelined memory architectures and test methodology are described. For a pipelined memory system performing at speed tests, the timing sequence for processing a test command comprises a precharge-read-precharge-write sequence for each clock cycle starting with the rising clock edge. The memory circuit utilizing this test command timing sequence comprises a sense amplifier and a single latch. The sense amplifier itself is used as a latch to implements scan functionality for the memory circuit. The memory device is incorporated into an integrated test wrapper circuit that executes back-to-back commands through serial compare operations using integrated scan flip-flop circuits. The test wrapper includes a fanout block and padded address scheme for testing multiple and disparate size memory devices in parallel.

Abstract: Embodiments of a random access memory word line driver circuit that reduces consumption of standby power are described. The word line driver is based on NOR-gate logic in which, for memory array consisting of a plurality of memory cells and word line drivers, given two inputs selected one word line goes high and the rest remain zero. The decoder circuit comprises two PMOS transistors in series with an NMOS-based inverter circuit. This arrangement reduces the leakage current through the NMOS transistor when the word line is not selected. An array of word line drivers incorporating a NOR-based decoder includes a shared pull up PMOS transistor for one of two address lines. The shared pull-up PMOS transistor is manufactured to a size on the order of at least two times the width of the remaining transistors of each word line stage.

Abstract: A method and apparatus for dual pass adaptive tessellation includes a vertex grouper tessellator operably coupled to receive primitive information and an index list and a shader processing unit coupled to the vertex grouper tessellator. During a first pass, the shader processing unit receives primitive indices generated from the primitive information and an auto-index value for each of the plurality of primitive indices. The method and apparatus further includes a plurality of vertex shader input staging registers operably coupled to the shader sequence, wherein the plurality of vertex shader input staging registers are coupled to a plurality of vertex shaders such that in response to a shader sequence output, the vertex shaders generate tessellation factors. The tessellation factors are provided to the vertex grouper tessellator such that the vertex grouper tessellator generates a per-process vector output, a per primitive output and a per packet output during a second pass.

Abstract: A memory architecture for use in a graphics processor including a main memory, a level one (L1) cache and a level two (L2) cache, coupled between the main memory and the L1 cache is disclosed. The L2 cache stores overlapping requests to the main memory before the requested information is stored in the L1 cache. In this manner, overlapping requests for previously stored information is retrieved from the faster L2 cache as opposed to the relatively slower main memory.

Abstract: A pseudo random number generator that generates a plurality of intermediate values, where each successive intermediate value is based, at least in part, on one of the succeeding intermediate values, where a final value based on a subset of the plurality of intermediate values. In application, the final value is based on performing a logical operation on the penultimate and last generated intermediate values.

Abstract: A method and apparatus for dual pass adaptive tessellation includes a vertex grouper tessellator operably coupled to receive primitive information and an index list and a shader processing unit coupled to the vertex grouper tessellator. During a first pass, the shader processing unit receives primitive indices generated from the primitive information and an auto-index value for each of the plurality of primitive indices. The method and apparatus further includes a plurality of vertex shader input staging registers operably coupled to the shader sequence, wherein the plurality of vertex shader input staging registers are coupled to a plurality of vertex shaders such that in response to a shader sequence output, the vertex shaders generate tessellation factors. The tessellation factors are provided to the vertex grouper tessellator such that the vertex grouper tessellator generates a per-process vector output, a per primitive output and a per packet output during a second pass.

Abstract: A secondary representative Z value memory includes a reduced-resolution representation of a primary representative Z value memory. Upon updating of a block of the primary representative Z value memory, one or more corresponding values are calculated for updating the reduced-resolution representation.

Abstract: A method and apparatus for producing a fragment descriptor for use in oversampling anti-aliasing includes processing that begins by generating a single representative color value for a plurality of subpixels of a pixel. The processing then continues by generating a single representative Z value for the pixel. The processing continues by generating masking information for the pixel, wherein the masking information indicates, for a given object-element being rendered, coverage of the pixel by the object-element. The processing continues by packing the single representative color value, the single representative Z value, and the masking information into a fragment descriptor. The processing continues by transporting the fragment descriptor to a custom memory. When the custom memory receives the fragment descriptor it unpacks it to recapture the single representative color value, the single representative Z value and the masking information.

Abstract: A method of graphics processing includes determining a non-depth conditional status and an occlusion status of a fragment. Such a method may be used in culling occluded fragments before expending resources such as processing cycles and memory bus usage. In one example, a scratchpad stores depth values of robust fragments and is used for occlusion testing. Graphics architectures, and methods that include use of representative Z values, are also disclosed.

Abstract: A method and apparatus for graphics processing using state and shader management includes at least one state and shader cache coupled to a compiler for compiling a hardware state and shader vector from an abstract state vector. Also included is an abstract state vector register containing the abstract state vector that is provided to the state and shader cache and the compiler. The state and shader cache receives the abstract state vector and determines whether a cache entry for that abstract state vector already exists. If the cache entry exists, the hardware state and shader vector is provided to hardware. If the entry does not exist, the state and shader cache provides a miss signal to the compiler, whereupon the compiler compiles the abstract state vector and generates a hardware state and shader vector. Thereupon the hardware state and shader vector is provided to the hardware.

Abstract: A graphics display system has a graphics processor system for forming a color image on a display, the display being composed of an array of pixels. A memory system has a first memory for storing at least respective color data and respective Z data that is render from primitives of the image, and a second memory for storing respective display data, derived from the rendered color data and Z data, for each of the pixels. The graphics processor system has a memory interface operatively connected to the first and second memories. During formation of an image frame, the memory interface writes to and reads from a Z buffer, and only writes to a render target color buffer. After the image is rendered, image data is copied from the first memory to the second memory from which the image is displayed.

Abstract: A logic enhanced memory that may be used in a video graphics system is presented. The logic enhanced memory includes an operation block that performs a number of operations on a block-by-block basis such that parallel processing results. The operations performed by the operation pipeline include blending operations for fragment blocks received from a graphics processing circuit, where the fragment blocks include pixel fragments generated by rendering graphics primitives. Other operations include selective reads and writes to the memory array, clearing functions, and swapping functions. Mask values included in the commands executed to control the operation pipeline allow for selectivity with respect to portions of the data packets, or blocks, to which the operations are applied.

Abstract: A method and apparatus for supporting anti-aliasing oversampling in a video graphics system that utilizes a custom memory for storage of the frame buffer is presented. The custom memory includes a memory array that stores the frame buffer as well as a data path that performs at least a portion of the blending operations associated with pixel fragments generated by a graphics processor. The fragments produced by a graphics processor are oversampled fragments such that each fragment may include a plurality of samples. If the sample set for a particular pixel location can be compressed, the compressed sample set is stored within the frame buffer of the custom memory circuit. However, if such compression is not possible, pointer information is stored within the frame buffer on the custom memory, and a sample memory controller included on the graphics processor maintains a complete sample set for the pixel location within a sample memory.

Abstract: A graphics pipeline, graphics processing system, and method for generating a screen image are disclosed that associate three-dimensional image data of multiple objects with respective screen pixels and determine the screen pixel characteristics in raster order.

Abstract: A method and system for processing textures for a graphical image on a display is disclosed. The graphical image includes an object. The object includes a plurality of fragments. The method and system include providing a memory and providing a plurality of texture processors coupled with the memory. The memory is for storing a portion of a program for processing a plurality of textures for the plurality of fragments. Each of the plurality of texture processors is for processing a texture for a fragment in accordance with the program. The plurality of texture processors is capable of processing a part of the plurality of textures in parallel.

Abstract: A method and system for generating a graphical display from data describing at least one three-dimensional object is disclosed. The method and system include providing a plurality of processors and a single interpolator coupled with the plurality of processors. Each of the processors receive a portion of the data for one of the three-dimensional object(s), determine if a current position is located within the portion of the data, and provide an output if the current position is located within the portion of the data. The single interpolator is configured to provide information relating to characteristics of the portion of the data in the processor in response to the processor providing the output.

Abstract: A system, method, and apparatus for compression of video data is presented. The compressed block includes a plurality of offset values, each indicating an offset between a corresponding one among the plurality of pixel values and a reference value. Exemplary methods are described wherein minimum and maximum reference values are derived from the block of pixel values, and a flag associated with each offset value indicates an appropriate reference value. Application of embodiments of the invention to the transfer of depth (Z) information are discussed.

Abstract: A method and apparatus for ensuring data coherency in a processing system that includes shared memory is presented. This is accomplished by including a hierarchical validity database within the core logic that interconnects the various memory clients to the memory structure. The hierarchical validity database stores a number of hierarchical levels, where each level pertains to different sized portions of the memory. Validity of a portion, or block, within the memory can be determined by referencing the hierarchical validity database.

Abstract: A method and apparatus for determining a rear most Z value for a pixel block is presented, where the pixel block is a portion of the image data for a frame as stored in a frame buffer. The frame buffer is stored in a DRAM memory structure that is included on an integrated circuit along with a render backend block that blends received fragments from a three-dimensional (3D) video graphics pipeline with the image data stored in the frame buffer. The 3D video graphics pipeline is located on a video graphics processing integrated circuit separate from the integrated circuit storing the frame buffer and render backend block. The integrated circuit storing the frame buffer includes a value determination block that determines the rear most Z value. The value determination block includes a data serialization block that serializes the bits corresponding to the Z values for the pixels included in the pixel block to produce a plurality of corresponding serial bit streams.

Abstract: A method and system for processing textures for a graphical image on a display is disclosed. The graphical image includes an object. The object includes a plurality of fragments. The method and system include providing a memory and providing a plurality of texture processors coupled with the memory. The memory is for storing a portion of a program for processing a plurality of textures for the plurality of fragments. Each of the plurality of texture processors is for processing a texture for a fragment in accordance with the program. The plurality of texture processors is capable of processing a part of the plurality of textures in parallel.