Patents by Inventor Stephen L. Runyon

Stephen L. Runyon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7882463
    Abstract: The invention includes a solution for selectively scaling an integrated circuit (IC) design by: layer, region or cell, or a combination of these. The selective scaling technique can be applied in a feedback loop with the manufacturing system with process and yield feedback, during the life of a design, to increase yield in early processes in such a way that hierarchy is preserved. The invention removes the need to involve designers in improving yield.
    Type: Grant
    Filed: February 22, 2008
    Date of Patent: February 1, 2011
    Assignee: International Business Machines Corporation
    Inventors: Fook-Luen Heng, Jason D. Hibbeler, Kevin W. McCullen, Rani R. Narayan, Stephen L. Runyon, Robert F. Walker
  • Patent number: 7865848
    Abstract: A method of layout optimization containing parameterized cells includes reading a physical design containing parameterized cells, creating a new version for each of usage of a given parameterized cell. The method optimizes physical design shapes of each new version of the parameterized cell by assigning variables to parameters of the parameterized cell according to a desired objective. Then, the method updates the parameters of each new version of the parameterized cell and replaces each new version of the parameterized cell with an instance of the parameterized cell having updated parameters. The method can optionally adjust physical design shapes based on constraints related to the parameters.
    Type: Grant
    Filed: August 28, 2007
    Date of Patent: January 4, 2011
    Assignee: International Business Machines Corporation
    Inventors: Veit Gernhoefer, Michael S. Gray, Matthew T. Guzowski, Jason D. Hibbeler, Stephen L. Runyon, Robert F. Walker, Bruce C. Wheeler
  • Patent number: 7627836
    Abstract: An iterative timing analysis is analytically performed before a chip is fabricated, based on a methodology using optical proximity correction techniques for shortening the gate lengths and adjusting metal line widths and proximity distances of critical time sensitive devices. The additional mask is used as a selective trim to form shortened gate lengths or wider metal lines for the selected, predetermined transistors, affecting the threshold voltages and the RC time constants of the selected devices. Marker shapes identify a predetermined subgroup of circuitry that constitutes the devices in the critical timing path. The analysis methodology is repeated as often as needed to improve the timing of the circuit with shortened designed gate lengths and modified RC timing constants until manufacturing limits are reached. A mask is made for the selected critical devices using OPC techniques.
    Type: Grant
    Filed: November 8, 2005
    Date of Patent: December 1, 2009
    Assignee: International Business Machines Corporation
    Inventors: James A. Culp, Lars W. Liebmann, Rajeev Malik, K. Paul Muller, Shreesh Narasimha, Stephen L. Runyon, Patrick M. Williams
  • Patent number: 7568173
    Abstract: Methods of independently migrating a hierarchical design are disclosed. A method for migrating a macro in an integrated circuit comprises: determining an interface strategy between a base cell in the macro and the macro, the base cell including an interface element involved in the interface strategy; migrating the base cell independently with respect to the macro based on the interface strategy; initially scaling the macro; swapping the migrated base cell into the macro; and legalizing content of the initially scaled macro.
    Type: Grant
    Filed: June 14, 2007
    Date of Patent: July 28, 2009
    Assignee: International Business Machines Corporation
    Inventors: Veit Gernhoefer, Matthew T. Guzowski, Jason D. Hibbeler, Kevin W. McCullen, Rani Narayan, Stephen L. Runyon, Leon J. Sigal, Robert F. Walker, Pieter J. Woeltgens, Xiaoyun K. Wu, Xin Yuan
  • Patent number: 7537997
    Abstract: Mechanisms for ensuring the migratability of circuits into future technologies while minimizing fabrication costs and maintaining or improving power efficiency are provided. A mask layer is introduced to portions of the integrated circuit prior to a stress inducing layer being applied to the integrated circuit. In an exemplary embodiment, a tensile or compressive film is applied to the devices on the integrated circuit chip but is removed from those devices whose operation is to be modified. Thereafter, a tensile or compressive strain layer is applied to the devices whose film was removed. An additional mask layer may then be used to effect a halo or well implant to relax the strain on the devices not being protected by the mask layer. In this way, the current of the non-protected devices is reduced back to its original target design point.
    Type: Grant
    Filed: May 5, 2008
    Date of Patent: May 26, 2009
    Assignee: International Business Machines Corporation
    Inventors: Stephen L. Runyon, Scott Stiffler
  • Publication number: 20090064061
    Abstract: A method of layout optimization containing parameterized cells includes reading a physical design containing parameterized cells, creating a new version for each of usage of a given parameterized cell. The method optimizes physical design shapes of each new version of the parameterized cell by assigning variables to parameters of the parameterized cell according to a desired objective. Then, the method updates the parameters of each new version of the parameterized cell and replaces each new version of the parameterized cell with an instance of the parameterized cell having updated parameters. The method can optionally adjust physical design shapes based on constraints related to the parameters.
    Type: Application
    Filed: August 28, 2007
    Publication date: March 5, 2009
    Inventors: Veit Gernhoefer, Michael S. Gray, Matthew T. Guzowski, Jason D. Hibbeler, Stephen L. Runyon, Robert F. Walker, Bruce C. Wheeler
  • Publication number: 20080313581
    Abstract: Methods of independently migrating a hierarchical design are disclosed. A method for migrating a macro in an integrated circuit comprises: determining an interface strategy between a base cell in the macro and the macro, the base cell including an interface element involved in the interface strategy; migrating the base cell independently with respect to the macro based on the interface strategy; initially scaling the macro; swapping the migrated base cell into the macro; and legalizing content of the initially scaled macro.
    Type: Application
    Filed: June 14, 2007
    Publication date: December 18, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veit Gernhoefer, Matthew T. Guzowski, Jason D. Hibbeler, Kevin W. McCullen, Rani Narayan, Stephen L. Runyon, Leon J. Sigal, Robert F. Walker, Pieter J. Woeltgens, Xiaoyun K. Wu, Xin Yuan
  • Publication number: 20080203489
    Abstract: Mechanisms for ensuring the migratability of circuits into future technologies while minimizing fabrication costs and maintaining or improving power efficiency are provided. A mask layer is introduced to portions of the integrated circuit prior to a stress inducing layer being applied to the integrated circuit. In an exemplary embodiment, a tensile or compressive film is applied to the devices on the integrated circuit chip but is removed from those devices whose operation is to be modified. Thereafter, a tensile or compressive strain layer is applied to the devices whose film was removed. An additional mask layer may then be used to effect a halo or well implant to relax the strain on the devices not being protected by the mask layer. In this way, the current of the non-protected devices is reduced back to its original target design point.
    Type: Application
    Filed: May 5, 2008
    Publication date: August 28, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen L. Runyon, Scott Stiffler
  • Publication number: 20080148210
    Abstract: The invention includes a solution for selectively scaling an integrated circuit (IC) design by: layer, region or cell, or a combination of these. The selective scaling technique can be applied in a feedback loop with the manufacturing system with process and yield feedback, during the life of a design, to increase yield in early processes in such a way that hierarchy is preserved. The invention removes the need to involve designers in improving yield.
    Type: Application
    Filed: February 22, 2008
    Publication date: June 19, 2008
    Inventors: Fook-Luen Heng, Jason D. Hibbeler, Kevin W. McCullen, Rani R. Narayan, Stephen L. Runyon, Robert F. Walker
  • Patent number: 7378318
    Abstract: A system and method for ensuring the migratability of circuits into future technologies while minimizing fabrication costs and maintaining or improving power efficiency are provided. A mask layer is introduced to portions of the integrated circuit prior to a stress inducing layer being applied to the integrated circuit. In an exemplary embodiment of the present invention, a tensile or compressive film is applied to the devices on the integrated circuit chip but is removed from those devices whose operation is to be modified. Thereafter, a tensile or compressive strain layer is applied to the devices whose film was removed. An additional mask layer may then be used to effect a halo or well implant to relax the strain on the devices not being protected by the mask layer. In this way, the current of the non-protected devices is reduced back to its original target design point.
    Type: Grant
    Filed: August 18, 2005
    Date of Patent: May 27, 2008
    Assignee: International Business Machines Corporation
    Inventors: Stephen L. Runyon, Scott Stiffler
  • Patent number: 7363601
    Abstract: Methods, systems and program products are disclosed for selectively scaling an integrated circuit (IC) design: by layer, by unit, or by ground rule, or a combination of these. The selective scaling technique can be applied in a feedback loop with the manufacturing system with process and yield feedback, during the life of a design, to increase yield in early processes in such a way that hierarchy is preserved. The invention removes the need to involve designers in improving yield where new technologies such as maskless fabrication are implemented.
    Type: Grant
    Filed: October 15, 2004
    Date of Patent: April 22, 2008
    Assignee: International Business Machines Corporation
    Inventors: Fook-Luen Heng, Jason D. Hibbeler, Kevin W. McCullen, Rani R. Narayan, Stephen L. Runyon, Robert F. Walker
  • Patent number: 5212662
    Abstract: A processor for performing floating point arithmetic operations is provided that includes a circuit that performs a first floating point arithmetic operation on a set of operands in a first cycle and and a second floating point arithmetic operation on an operand and a result of the first floating point arithmetic operation during a second cycle. A control circuit is provided for, in a third cycle, transferring a result of the second floating operation to the first floating point circuit for a first floating point operation in a next successive cycle while rounding the result of the second floating point operation.
    Type: Grant
    Filed: September 11, 1990
    Date of Patent: May 18, 1993
    Assignee: International Business Machines Corporation
    Inventors: Daniel Cocanougher, Robert K. Montoye, Myhong Nguyenphu, Stephen L. Runyon
  • Patent number: 4999802
    Abstract: A processor for performing floating point arithmetic operations is provided that includes a circuit that performs a first floating point arithmetic operation on a set of operands in a first cycle and a second floating point arithmetic operation on an operand and a result of the first floating point arithmetic operation during a second cycle. A control circuit is provided for, in a third cycle, transferring a result of the second floating operation to the first floating point circuit for a first floating point operation in a next successive cycle while rounding the result of the second floating point operation.
    Type: Grant
    Filed: January 13, 1989
    Date of Patent: March 12, 1991
    Assignee: International Business Machines Corporation
    Inventors: Daniel Cocanougher, Robert K. Montoye, Myhong Nguyenphu, Stephen L. Runyon