Abstract: A method for efficiently using a large secondary cache is disclosed herein. In certain embodiments, such a method may include accumulating, in a secondary cache, a plurality of data tracks. These data tracks may include modified data and/or unmodified data. The method may determine if a subset of the plurality of data tracks makes up a full stride. In the event the subset makes up a full stride, the method may destage the subset from the secondary cache. By destaging full strides, the method reduces the number of disk operations that are required to destage data from the secondary cache. A corresponding computer program product and apparatus are also disclosed herein.

Abstract: A method for efficiently using a large secondary cache is disclosed herein. In certain embodiments, such a method may include accumulating, in a secondary cache, a plurality of data tracks. These data tracks may include modified data and/or unmodified data. The method may determine if a subset of the plurality of data tracks makes up a full stride. In the event the subset makes up a full stride, the method may destage the subset from the secondary cache. By destaging full strides, the method reduces the number of disk operations that are required to destage data from the secondary cache. A corresponding computer program product and apparatus are also disclosed and claimed herein.

Abstract: In one aspect of the present description, in response to detection of a failure of a root server of a storage controller, a switch for input/output adapters may be reconfigured to report errors to a successor root server without reinitializing the input/output adapters. Other features and aspects may be realized, depending upon the particular application.

Abstract: A method of providing error notification in a storage subsystem includes writing a first defined value by a host adapter of the storage subsystem to a system management interrupt (SMI) register to generate a hardware interrupt, registering and handling the hardware interrupt by a kernel module of the storage subsystem, writing a second defined value to a shared memory location of the storage subsystem by the kernel module, and reading a shared memory offset value by the host adapter. A system for providing error notification in a storage subsystem includes a controller including a serial management interface (SMI) register subcomponent, a first processing component connected to the controller having a kernel module, and a second processing component connected to the controller executing host adapter software.

Abstract: In managing multiprocessor operations, a first processor repetitively reads a cache line wherein the cache line is cached from a line of a shared memory of resources shared by both the first processor and a second processor. Coherency is maintained between the shared memory line and the cache line in accordance with a cache coherency protocol. In one aspect, the repetitive cache line reading occupies the first processor and inhibits the first processor from accessing the shared resources. In another aspect, upon completion of operations by the second processor involving the shared resources, the second processor writes data to the shared memory line to signal to the first processor that the shared resources may be accessed by the first processor. In response, the first processor changes the state of the cache line in accordance with the cache coherency protocol and reads the data written by the second processor. Other embodiments are described and claimed.

Abstract: Provided are a method, system, deployment and article of manufacture, wherein in one embodiment, a mode of operation may be switched to a service mode by detecting a device inserted into a connector of an input/output port of a system. In the illustrated embodiment, the device has a connector and a wire which loops a code received from the input/output port back to the input/output port. Upon detecting receipt of the transmitted code, the mode of operation may be switched to a service mode. Other embodiments are described and claimed.

Abstract: In one embodiment, a first processor of a multiprocessor system, encounters an exception and jumps to exception handler code at an architecture-defined exception vector. The processor is directed to a data structure which provides a programmable exception vector to additional exception handler code. This additional code may be executed as if it were located at the architecture-defined exception vector. Other embodiments are described and claimed.

Abstract: In managing multiprocessor operations, a first processor repetitively reads a cache line wherein the cache line is cached from a line of a shared memory of resources shared by both the first processor and a second processor. Coherency is maintained between the shared memory line and the cache line in accordance with a cache coherency protocol. In one aspect, the repetitive cache line reading occupies the first processor and inhibits the first processor from accessing the shared resources. In another aspect, upon completion of operations by the second processor involving the shared resources, the second processor writes data to the shared memory line to signal to the first processor that the shared resources may be accessed by the first processor. In response, the first processor changes the state of the cache line in accordance with the cache coherency protocol and reads the data written by the second processor. Other embodiments are described and claimed.

Abstract: In managing multiprocessor operations, a first processor repetitively reads a cache line wherein the cache line is cached from a line of a shared memory of resources shared by both the first processor and a second processor. Coherency is maintained between the shared memory line and the cache line in accordance with a cache coherency protocol. In one aspect, the repetitive cache line reading occupies the first processor and inhibits the first processor from accessing the shared resources. In another aspect, upon completion of operations by the second processor involving the shared resources, the second processor writes data to the shared memory line to signal to the first processor that the shared resources may be accessed by the first processor. In response, the first processor changes the state of the cache line in accordance with the cache coherency protocol and reads the data written by the second processor. Other embodiments are described and claimed.

Abstract: A method of providing error notification in a storage subsystem includes writing a first defined value by a host adapter of the storage subsystem to a system management interrupt (SMI) register to generate a hardware interrupt, registering and handling the hardware interrupt by a kernel module of the storage subsystem, writing a second defined value to a shared memory location of the storage subsystem by the kernel module, and reading a shared memory offset value by the host adapter. A system for providing error notification in a storage subsystem includes a controller including a serial management interface (SMI) register subcomponent, a first processing component connected to the controller having a kernel module, and a second processing component connected to the controller executing host adapter software.

Abstract: Provided are a method, system, deployment and article of manufacture, wherein in one embodiment, a mode of operation may be switched to a service mode by detecting a device inserted into a connector of an input/output port of a system. In the illustrated embodiment, the device has a connector and a wire which loops a code received from the input/output port back to the input/output port. Upon detecting receipt of the transmitted code, the mode of operation may be switched to a service mode. Other embodiments are described and claimed.

Abstract: An apparatus, system, and method are disclosed for flushing cache data in a cache system. The apparatus includes a zero module and a flush module. The zero module executes an internal processor instruction to zero out a zero memory segment of a nonvolatile memory and a processor cache in response to a loss of primary power to the processor cache. The flush module flushes modified data from an address in the processor cache to a flush memory segment of the nonvolatile memory before the zero module puts a zero in the address. Advantageously, the zero memory segment is reserved within the memory and used to zero out the processor cache, effectively flushing the existing data from the processor cache to a flush memory segment of the memory.