Patents by Inventor Stephen Lee Smith

Stephen Lee Smith has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11410124
    Abstract: It may be determined that a material package has been used by determining that the material package has moved from a previously recorded location based upon location data corresponding to the material package and a beacon code. The location data may correspond to the material package and the beacon code being periodically reported by a beacon located proximate to the material package. Next, a weight of the material package that has been used subsequent to the material package being used may be received and, based upon the beacon code and in response to receiving the weight of the material package; the material database for a material package record may be queried. A remaining amount of material corresponding to the material package may be calculated based upon the received weight and data from the material package record found from the material package record.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: August 9, 2022
    Assignee: SOUTHWIRE COMPANY, LLC
    Inventors: Stephen Lee Spruell, Charles A. Murrah, Jr., Carter Edward Smith
  • Patent number: 11249813
    Abstract: Roughly described, a task control system for managing multi-scale simulations receives a case/task list which identifies cases to be evaluated, at least one task for each of the cases, and dependencies among the tasks. A module allocates available processor cores to at least some of the tasks, constrained by the dependencies, and initiates execution of the tasks on allocated cores. A module, in response to completion of a particular one of the tasks, determines whether or not the result of the task warrants stopping or pruning tasks, and if so, then terminates or prunes one or more of the uncompleted tasks in the case/task list. A module also re-allocates available processor cores to pending not-yet-executing tasks in accordance with time required to complete the tasks and constrained by the dependencies, and initiates execution of the tasks on allocated cores.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: February 15, 2022
    Assignee: Synopsys, Inc.
    Inventors: Stephen Lee Smith, Michael C. Shaughnessy-Culver, Jie Liu, Victor Moroz, Yong-Seog Oh, Pratheep Balasingam, Terry Sylvan Kam-Chiu Ma
  • Patent number: 10831957
    Abstract: Electronic design automation modules for simulate the behavior of structures and materials at multiple simulation scales with different simulation modules.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: November 10, 2020
    Assignee: Synopsys, Inc.
    Inventors: Jie Liu, Victor Moroz, Michael C. Shaughnessy-Culver, Stephen Lee Smith, Yong-Seog Oh, Pratheep Balasingam, Terry Sylvan Kam-Chiu Ma
  • Patent number: 10776560
    Abstract: A system for evaluating candidate materials for fabrication of integrated circuits includes a data processor coupled to a memory. Roughly described, the data processor is configured to: calculate and write to a first database, for each of a plurality of candidate materials, values for each property in a set of intermediate properties; calculate and write to a second database, values for a selected target property for various combinations of values for the intermediate properties and values describing candidate environments; and for a particular candidate material and a particular environment in combination, determine values for the intermediate properties for the candidate material by reference to the first database, and determine the value of the target property for the candidate material by querying the second database with, in combination, (1) the determined intermediate property values of the candidate material and (2) a value or values describing the particular environment.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: September 15, 2020
    Assignee: Synopsys, Inc.
    Inventors: Victor Moroz, Stephen Lee Smith, Yong-Seog Oh, Michael C. Shaughnessy-Culver, Jie Liu, Terry Sylvan Kam-Chiu Ma
  • Patent number: 10706209
    Abstract: Roughly described, a system for estimating an effective channel length of a 3D transistor having a gate length below 20 nm involves estimating an effective volume of the channel and a cross-sectional area of the channel, and estimating the effective channel length as the ratio of effective volume to cross-sectional area. Preferably the effective volume is estimated as the sum of the Voronoi volumes within containing boundaries of the channel, excluding those volumes having a dopant concentration above the source/drain dopant concentration at the carrier injection point. The containing boundaries can be identified using geometry data describing the transistor, particularly the data identifying inner surfaces of the gate dielectric. The estimated effective channel length can be used in TCAD level analysis of the transistor and calculating characteristics of the transistor as needed for circuit simulation.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: July 7, 2020
    Assignee: Synopsys, Inc.
    Inventors: Victor Moroz, Yong-Seog Oh, Stephen Lee Smith, Michael C. Shaughnessy-Culver, Jie Liu
  • Patent number: 10685156
    Abstract: Electronic design automation modules include a first tool and a second tool. The first tool includes ab initio simulation procedures configured to use input parameters to produce information about a band structure of a simulated material on a first simulation scale specified at least in part by the input parameters. The second tool includes a simulation procedure configured to used information about the band structure of the simulated material produced by the first tool to extract parameters on a second simulation scale larger than the first simulation scale.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: June 16, 2020
    Assignee: SYNOPSYS, INC.
    Inventors: Jie Liu, Victor Moroz, Michael C Shaughnessy-Culver, Stephen Lee Smith, Yong-Seog Oh, Pratheep Balasingam, Terry Sylvan Kam-Chiu Ma
  • Patent number: 10606968
    Abstract: Roughly described, a system for simulating a temporal process in a body includes a meshing module to impose a grid of nodes on the body, the grid having a uniform node spacing which is less than the quantum separation distance in silicon. A system of node equations is provided, including at least one node equation for each of a plurality of nodes of the grid. The node equations describe behavior of at least one physical quantity at that node through each time step of the process. An iterating module iterates through the time steps to determine values for physical quantities of the body at the end of the simulation period. Preferably one particle of the body is assigned to each node of the grid. For moving boundary processes, boundary movement can be represented simply by changing the particle type assigned to various nodes of the grid as the boundary advances.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: March 31, 2020
    Assignee: SYNOPSYS, INC.
    Inventors: Victor Moroz, Stephen Lee Smith
  • Publication number: 20200089543
    Abstract: Roughly described, a task control system for managing multi-scale simulations receives a case/task list which identifies cases to be evaluated, at least one task for each of the cases, and dependencies among the tasks. A module allocates available processor cores to at least some of the tasks, constrained by the dependencies, and initiates execution of the tasks on allocated cores. A module, in response to completion of a particular one of the tasks, determines whether or not the result of the task warrants stopping or pruning tasks, and if so, then terminates or prunes one or more of the uncompleted tasks in the case/task list. A module also re-allocates available processor cores to pending not-yet-executing tasks in accordance with time required to complete the tasks and constrained by the dependencies, and initiates execution of the tasks on allocated cores.
    Type: Application
    Filed: November 22, 2019
    Publication date: March 19, 2020
    Applicant: Synopsys, Inc.
    Inventors: Stephen Lee Smith, Michael C. Shaughnessy-Culver, Jie Liu, Victor Moroz, Yong-Seog Oh, Pratheep Balasingam, Terry Sylvan Kam-Chiu Ma
  • Publication number: 20200089841
    Abstract: A system for evaluating candidate materials for fabrication of integrated circuits includes a data processor coupled to a memory. Roughly described, the data processor is configured to: calculate and write to a first database, for each of a plurality of candidate materials, values for each property in a set of intermediate properties; calculate and write to a second database, values for a selected target property for various combinations of values for the intermediate properties and values describing candidate environments; and for a particular candidate material and a particular environment in combination, determine values for the intermediate properties for the candidate material by reference to the first database, and determine the value of the target property for the candidate material by querying the second database with, in combination, (1) the determined intermediate property values of the candidate material and (2) a value or values describing the particular environment.
    Type: Application
    Filed: November 21, 2019
    Publication date: March 19, 2020
    Applicant: Synopsys, Inc.
    Inventors: Victor Moroz, Stephen Lee Smith, Yong-Seog Oh, Michael C. Shaughnessy-Culver, Jie Liu, Terry Sylvan Kam-Chiu Ma
  • Publication number: 20200004922
    Abstract: Roughly described, a system for estimating an effective channel length of a 3D transistor having a gate length below 20 nm involves estimating an effective volume of the channel and a cross-sectional area of the channel, and estimating the effective channel length as the ratio of effective volume to cross-sectional area. Preferably the effective volume is estimated as the sum of the Voronoi volumes within containing boundaries of the channel, excluding those volumes having a dopant concentration above the source/drain dopant concentration at the carrier injection point. The containing boundaries can be identified using geometry data describing the transistor, particularly the data identifying inner surfaces of the gate dielectric. The estimated effective channel length can be used in TCAD level analysis of the transistor and calculating characteristics of the transistor as needed for circuit simulation.
    Type: Application
    Filed: September 11, 2019
    Publication date: January 2, 2020
    Applicant: Synopsys, Inc.
    Inventors: Victor Moroz, Yong-Seog Oh, Stephen Lee Smith, Michael C. Shaughnessy-Culver, Jie Liu
  • Patent number: 10516725
    Abstract: Roughly described, a technique for approximating a target property of a target material is provided. For each material in a plurality of anchor materials, a correspondence is provided between the value for a predetermined index property of the material and a value for the target property of the material, the values of all the index properties being different. A predictor function is identified in dependence upon the correspondence. A computer system determines a value for the target property for the target material in dependence upon the predictor function and a value for the index property for the target material. The determined value for the target property for the target material is reported to a user. The correspondence can be provided in a database on a non-transitory computer readable medium. The correspondence can be determined experimentally or analytically for each material in a plurality of anchor materials.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: December 24, 2019
    Assignee: SYNOPSYS, INC.
    Inventors: Victor Moroz, Stephen Lee Smith, Yong-Seog Oh, Jie Liu, Michael C. Shaughnessy-Culver, Terry Sylvan Kam-Chiu Ma
  • Patent number: 10489212
    Abstract: Roughly described, a task control system for managing multi-scale simulations receives a case/task list which identifies cases to be evaluated, at least one task for each of the cases, and dependencies among the tasks. A module allocates available processor cores to at least some of the tasks, constrained by the dependencies, and initiates execution of the tasks on allocated cores. A module, in response to completion of a particular one of the tasks, determines whether or not the result of the task warrants stopping or pruning tasks, and if so, then terminates or prunes one or more of the uncompleted tasks in the case/task list. A module also re-allocates available processor cores to pending not-yet-executing tasks in accordance with time required to complete the tasks and constrained by the dependencies, and initiates execution of the tasks on allocated cores.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: November 26, 2019
    Assignee: SYNOPSYS, INC.
    Inventors: Stephen Lee Smith, Michael C. Shaughnessy-Culver, Jie Liu, Victor Moroz, Yong-Seog Oh, Pratheep Balasingam, Terry Sylvan Kam-Chiu Ma
  • Patent number: 10417373
    Abstract: Roughly described, a system for estimating an effective channel length of a 3D transistor having a gate length below 20 nm involves estimating an effective volume of the channel and a cross-sectional area of the channel, and estimating the effective channel length as the ratio of effective volume to cross-sectional area. Preferably the effective volume is estimated as the sum of the Voronoi volumes within containing boundaries of the channel, excluding those volumes having a dopant concentration above the source/drain dopant concentration at the carrier injection point. The containing boundaries can be identified using geometry data describing the transistor, particularly the data identifying inner surfaces of the gate dielectric. The estimated effective channel length can be used in TCAD level analysis of the transistor and calculating characteristics of the transistor as needed for circuit simulation.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: September 17, 2019
    Assignee: SYNOPSYS, INC.
    Inventors: Victor Moroz, Yong-Seog Oh, Stephen Lee Smith, Michael C. Shaughnessy-Culver, Jie Liu
  • Patent number: 10402520
    Abstract: An electronic design automation tool includes an application program interface API. The API includes a set of parameters and procedures supporting atomistic scale modeling of electronic materials. The procedures include a procedure to execute first principles calculations, a procedure to process results from the first principles calculations to extract device scale parameters from the results, and a procedure to determine whether the device scale parameters extracted from the results lie within a specified range of the stored information for the material. The procedures also include a procedure to parameterize an input parameter of a first principles procedure, including a procedure to execute a set of DFT computations across an input parameter space to characterize sensitivity of one of the intermediate parameter and the output parameter. Also included is a procedure to execute a second set of DFT computations across a refined input parameter space.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: September 3, 2019
    Assignee: SYNOPSYS, INC.
    Inventors: Yong-Seog Oh, Michael C. Shaughnessy-Culver, Stephen Lee Smith, Jie Liu, Victor Moroz, Pratheep Balasingam, Terry Sylvan Kam-Chiu Ma
  • Publication number: 20190147123
    Abstract: Roughly described, a system for simulating a temporal process in a body includes a meshing module to impose a grid of nodes on the body, the grid having a uniform node spacing which is less than the quantum separation distance in silicon. A system of node equations is provided, including at least one node equation for each of a plurality of nodes of the grid. The node equations describe behavior of at least one physical quantity at that node through each time step of the process. An iterating module iterates through the time steps to determine values for physical quantities of the body at the end of the simulation period. Preferably one particle of the body is assigned to each node of the grid. For moving boundary processes, boundary movement can be represented simply by changing the particle type assigned to various nodes of the grid as the boundary advances.
    Type: Application
    Filed: October 12, 2018
    Publication date: May 16, 2019
    Applicant: Synopsys, Inc.
    Inventors: Victor Moroz, Stephen Lee Smith
  • Patent number: 10102318
    Abstract: Roughly described, a system for simulating a temporal process in a body includes a meshing module to impose a grid of nodes on the body, the grid having a uniform node spacing which is less than the quantum separation distance in silicon. A system of node equations is provided, including at least one node equation for each of a plurality of nodes of the grid. The node equations describe behavior of at least one physical quantity at that node through each time step of the process. An iterating module iterates through the time steps to determine values for physical quantities of the body at the end of the simulation period. Preferably one particle of the body is assigned to each node of the grid. For moving boundary processes, boundary movement can be represented simply by changing the particle type assigned to various nodes of the grid as the boundary advances.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: October 16, 2018
    Assignee: Synopsys, Inc.
    Inventors: Victor Moroz, Stephen Lee Smith
  • Patent number: 10049173
    Abstract: Electronic design automation to simulate the behavior of structures and materials at multiple simulation scales with different simulators.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: August 14, 2018
    Assignee: Synopsys, Inc.
    Inventors: Jie Liu, Victor Moroz, Michael C. Shaughnessy-Culver, Stephen Lee Smith, Yong-Seog Oh, Pratheep Balasingam, Terry Sylvan Kam-Chiu Ma
  • Publication number: 20180144076
    Abstract: Electronic design automation modules for simulate the behavior of structures and materials at multiple simulation scales with different simulation modules.
    Type: Application
    Filed: January 3, 2018
    Publication date: May 24, 2018
    Applicant: Synopsys, Inc.
    Inventors: Jie Liu, Victor Moroz, Michael C. Shaughnessy-Culver, Stephen Lee Smith, Yong-Seog Oh, Pratheep Balasingam, Terry Sylvan Kam-Chiu Ma
  • Publication number: 20180113968
    Abstract: Roughly described, a system for simulating a temporal process in a body includes a meshing module to impose a grid of nodes on the body, the grid having a uniform node spacing which is less than the quantum separation distance in silicon. A system of node equations is provided, including at least one node equation for each of a plurality of nodes of the grid. The node equations describe behavior of at least one physical quantity at that node through each time step of the process. An iterating module iterates through the time steps to determine values for physical quantities of the body at the end of the simulation period. Preferably one particle of the body is assigned to each node of the grid. For moving boundary processes, boundary movement can be represented simply by changing the particle type assigned to various nodes of the grid as the boundary advances.
    Type: Application
    Filed: December 13, 2017
    Publication date: April 26, 2018
    Applicant: Synopsys, Inc.
    Inventors: Victor Moroz, Stephen Lee Smith
  • Patent number: 9881111
    Abstract: Electronic design automation modules for simulate the behavior of structures and materials at multiple simulation scales with different simulation modules.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: January 30, 2018
    Assignee: SYNOPSYS, INC.
    Inventors: Jie Liu, Victor Moroz, Michael C. Shaughnessy-Culver, Stephen Lee Smith, Yong-Seog Oh, Pratheep Balasingam, Terry Sylvan Kam-Chiu Ma