Patents by Inventor Stephen Lewis Moore
Stephen Lewis Moore has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11295053Abstract: Various implementations described herein are directed to an integrated circuit (IC) having a design that is severable into multiple sub-circuits having input-output (IO) ports. The integrated circuit (IC) may include multiple physical electrical connections that are adapted to electrically interconnect the IO ports of the multiple sub-circuits to operate as the IC, and the IO ports have three-dimensional (3D) geometric position information associated therewith.Type: GrantFiled: September 12, 2019Date of Patent: April 5, 2022Assignee: Arm LimitedInventors: Xiaoqing Xu, Brian Tracy Cline, Saurabh Pijuskumar Sinha, Stephen Lewis Moore, Mudit Bhargava
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Patent number: 11126778Abstract: Implementations described herein are directed to a device with a processor and memory having stored thereon instructions that, when executed by the processor, cause the processor to acquire an integrated circuit layout of physical cells from a database and define wirelength relationships between input/output connections and a cell count for the physical cells in multiple domains. The instructions may cause the processor to define wirelength parameters of the integrated circuit layout in each domain of the multiple domains and generate a data file for the integrated circuit layout of the physical cells based on the wirelength relationships and the wirelength parameters to guide power and performance of the integrated circuit layout of the physical cells. The instructions may cause the processor to fabricate, or contribute to the fabrication of, an integrated circuit based on the data file for the integrated circuit layout of the physical cells.Type: GrantFiled: May 18, 2020Date of Patent: September 21, 2021Assignee: Arm LimitedInventors: Divya Madapusi Srinivas Prasad, Saurabh Pijuskumar Sinha, Brian Tracy Cline, Stephen Lewis Moore
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Patent number: 11120191Abstract: Various implementations described herein are directed to a method that defines tiers of an integrated circuit having standard cells placed adjacent to each other in a multi-tier placement. The integrated circuit includes multi-tier nets connected with inter-tier connections. The method includes pairing inter-tier connections as inter-tier-connection pairs belonging to a same net. The method includes grouping standard cells in groups with or without inter-tier-connection pairs from the tiers. The method includes relating the standard cells with or without inter-tier-connection pairs within each group from the groups by generating a multi-tier fence boundary around physical locations of the standard cells with or without inter-tier-connection pairs.Type: GrantFiled: March 16, 2020Date of Patent: September 14, 2021Assignee: Arm LimitedInventors: Xiaoqing Xu, Brian Tracy Cline, Stephen Lewis Moore, Saurabh Pijuskumar Sinha
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Publication number: 20210081508Abstract: Various implementations described herein are directed to an integrated circuit (IC) having a design that is severable into multiple sub-circuits having input-output (IO) ports. The integrated circuit (IC) may include multiple physical electrical connections that are adapted to electrically interconnect the IO ports of the multiple sub-circuits to operate as the IC, and the IO ports have three-dimensional (3D) geometric position information associated therewith.Type: ApplicationFiled: September 12, 2019Publication date: March 18, 2021Inventors: Xiaoqing Xu, Brian Tracy Cline, Saurabh Pijuskumar Sinha, Stephen Lewis Moore, Mudit Bhargava
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Publication number: 20200279067Abstract: Implementations described herein are directed to a device with a processor and memory having stored thereon instructions that, when executed by the processor, cause the processor to acquire an integrated circuit layout of physical cells from a database and define wirelength relationships between input/output connections and a cell count for the physical cells in multiple domains. The instructions may cause the processor to define wirelength parameters of the integrated circuit layout in each domain of the multiple domains and generate a data file for the integrated circuit layout of the physical cells based on the wirelength relationships and the wirelength parameters to guide power and performance of the integrated circuit layout of the physical cells. The instructions may cause the processor to fabricate, or contribute to the fabrication of, an integrated circuit based on the data file for the integrated circuit layout of the physical cells.Type: ApplicationFiled: May 18, 2020Publication date: September 3, 2020Inventors: Divya Madapusi Srinivas Prasad, Saurabh Pijuskumar Sinha, Brian Tracy Cline, Stephen Lewis Moore
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Publication number: 20200218845Abstract: Various implementations described herein are directed to a method that defines tiers of an integrated circuit having standard cells placed adjacent to each other in a multi-tier placement. The integrated circuit includes multi-tier nets connected with inter-tier connections. The method includes pairing inter-tier connections as inter-tier-connection pairs belonging to a same net. The method includes grouping standard cells in groups with or without inter-tier-connection pairs from the tiers. The method includes relating the standard cells with or without inter-tier-connection pairs within each group from the groups by generating a multi-tier fence boundary around physical locations of the standard cells with or without inter-tier-connection pairs.Type: ApplicationFiled: March 16, 2020Publication date: July 9, 2020Inventors: Xiaoqing Xu, Brian Tracy Cline, Stephen Lewis Moore, Saurabh Pijuskumar Sinha
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Patent number: 10657218Abstract: Implementations described herein are directed to a device with a processor and memory having stored thereon instructions that, when executed by the processor, cause the processor to acquire an integrated circuit layout of physical cells from a database and define wirelength relationships between input/output connections and a cell count for the physical cells in multiple domains. The instructions may cause the processor to define wirelength parameters of the integrated circuit layout in each domain of the multiple domains and generate a data file for the integrated circuit layout of the physical cells based on the wirelength relationships and the wirelength parameters to guide power and performance of the integrated circuit layout of the physical cells. The instructions may cause the processor to fabricate, or contribute to the fabrication of, an integrated circuit based on the data file for the integrated circuit layout of the physical cells.Type: GrantFiled: November 29, 2017Date of Patent: May 19, 2020Assignee: Arm LimitedInventors: Divya Madapusi Srinivas Prasad, Saurabh Pijuskumar Sinha, Brian Tracy Cline, Stephen Lewis Moore
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Patent number: 10599806Abstract: Various implementations described herein are directed to a method that defines tiers of an integrated circuit having standard cells placed adjacent to each other in a multi-tier placement. The integrated circuit includes multi-tier nets connected with inter-tier connections. The method includes pairing inter-tier connections as inter-tier-connection pairs belonging to a same net. The method includes grouping standard cells in groups with or without the inter-tier-connection pairs from the tiers. The method includes relating the standard cells with or without the inter-tier-connection pairs within each group from the groups by generating a multi-tier fence boundary around physical locations of the standard cells with or without the inter-tier-connection pairs.Type: GrantFiled: March 28, 2018Date of Patent: March 24, 2020Assignee: Arm LimitedInventors: Xiaoqing Xu, Brian Tracy Cline, Stephen Lewis Moore, Saurabh Pijuskumar Sinha
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Publication number: 20190303523Abstract: Various implementations described herein are directed to a method that defines tiers of an integrated circuit having standard cells placed adjacent to each other in a multi-tier placement. The integrated circuit includes multi-tier nets connected with inter-tier connections. The method includes pairing inter-tier connections as inter-tier-connection pairs belonging to a same net. The method includes grouping standard cells in groups with or without inter-tier-connection pairs from the tiers. The method includes relating the standard cells with or without inter-tier-connection pairs within each group from the groups by generating a multi-tier fence boundary around physical locations of the standard cells with or without inter-tier-connection pairs.Type: ApplicationFiled: March 28, 2018Publication date: October 3, 2019Inventors: Xiaoqing Xu, Brian Tracy Cline, Stephen Lewis Moore, Saurabh Pijuskumar Sinha
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Publication number: 20190163860Abstract: Implementations described herein are directed to a device with a processor and memory having stored thereon instructions that, when executed by the processor, cause the processor to acquire an integrated circuit layout of physical cells from a database and define wirelength relationships between input/output connections and a cell count for the physical cells in multiple domains. The instructions may cause the processor to define wirelength parameters of the integrated circuit layout in each domain of the multiple domains and generate a data file for the integrated circuit layout of the physical cells based on the wirelength relationships and the wirelength parameters to guide power and performance of the integrated circuit layout of the physical cells. The instructions may cause the processor to fabricate, or contribute to the fabrication of, an integrated circuit based on the data file for the integrated circuit layout of the physical cells.Type: ApplicationFiled: November 29, 2017Publication date: May 30, 2019Inventors: Divya Madapusi Srinivas Prasad, Saurabh Pijuskumar Sinha, Brian Tracy Cline, Stephen Lewis Moore
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Patent number: 10114918Abstract: Various implementations described herein are directed to systems and methods for controlling physical placement of a circuit design. The systems and methods may extract state groups of the circuit design by deriving state groups from each logical hierarchy of the circuit design. At each level, available state points may be grouped by similarity and stored in a state groups collection alongside grouping terms. The systems and methods may generate a state bounds file that bounds locations of the state points in the circuit design. The state bounds file may be based on the extracted state groups and the grouping terms stored in the state groups collection. The systems and methods may control physical placement of the circuit design using the state bounds file.Type: GrantFiled: January 27, 2016Date of Patent: October 30, 2018Assignee: ARM LimitedInventor: Stephen Lewis Moore
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Publication number: 20170212975Abstract: Various implementations described herein are directed to systems and methods for controlling physical placement of a circuit design. The systems and methods may extract state groups of the circuit design by deriving state groups from each logical hierarchy of the circuit design. At each level, available state points may be grouped by similarity and stored in a state groups collection alongside grouping terms. The systems and methods may generate a state bounds file that bounds locations of the state points in the circuit design. The state bounds file may be based on the extracted state groups and the grouping terms stored in the state groups collection. The systems and methods may control physical placement of the circuit design using the state bounds file.Type: ApplicationFiled: January 27, 2016Publication date: July 27, 2017Inventor: Stephen Lewis Moore