Patents by Inventor Stephen Luce

Stephen Luce has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7690495
    Abstract: The present invention relates to a card reader assembly. The card reader assembly can be mounted in a variety of vending equipment, arcade game equipment, and other suitable equipment. Furthermore, the card reader assembly can be mounted in a standard size vending machine bill validator opening. The card reader assembly can provide for the optional mounting of a card reader, a card reader interface circuit board, a payment module board, a communication board, and or a printer. The printer mechanism is mounted on a printer bracket. The printer bracket can be slid over the edges of and fastened to the support bracket. A paper exit slot can be provided in the card reader assembly faceplate to allow the printer paper to exit through the faceplate such that a user can receive the printer paper. In addition, the printer mechanism, card reader, and or a pushbutton can be electrically connected to the card reader interface board.
    Type: Grant
    Filed: October 22, 2002
    Date of Patent: April 6, 2010
    Assignee: USA Technologies, Inc.
    Inventors: H. Brock Kolls, Stephen Luce, Barry J. Patrizzi
  • Publication number: 20080073742
    Abstract: An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip to backside metallurgy on the imaging chip. The backside metallurgy of the imaging chip is connected to metallurgy on the active surface of the logic chip using an array of solder bumps in BGA fashion. The interconnection arrangement provides a CSP which matches the space constraints of a cell phone, for example. The arrangement also utilizes minimal wire lengths for reduced noise. Connection of the CSP to a carrier package may be either by conductive through vias or wire bonding. The CSP is such that the imaging chip may readily be mounted across an aperture in the wall of a cell phone, for example, so as to expose the light sensitive pixels on the active surface of said imaging chip to light.
    Type: Application
    Filed: November 20, 2007
    Publication date: March 27, 2008
    Inventors: James Adkisson, Jeffrey Gambino, Mark Jaffe, Robert Leidy, Stephen Luce, Richard Rassell, Edmund Sprogis
  • Publication number: 20080064189
    Abstract: A crack stop for low K dielectric materials of an integrated circuit (IC) formed on an IC chip using metal interconnects which do not form a self-passivating oxide layer, such as copper or silver interconnects, in a low-K dielectric material to prevent damage to the active area of the IC chip caused by chipping and cracking formed along peripheral edges of the IC chip during a dicing operation. A moisture barrier or edge seal is formed as a metal stack positioned along the outer peripheral edges of the active area of the IC chip. The crack stop is formed by at least one trench or groove positioned outside of the moisture barrier/edge seal on the outer periphery of the IC chip.
    Type: Application
    Filed: October 31, 2007
    Publication date: March 13, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Timothy Daubenspeck, Jeffrey Gambino, Stephen Luce, Thomas McDevitt, William Motsiff, Mark Pouliot, Jennifer Robbins
  • Publication number: 20070132067
    Abstract: Structures for aligning wafers and methods for operating the same. The structure includes (a) a first semiconductor wafer including a first capacitive coupling structure, and (b) a second semiconductor wafer including a second capacitive coupling structure. The first and second semiconductor wafers are in direct physical contact with each other via a common surface. If the first and second semiconductor wafers are moved with respect to each other by a first displacement distance of 1 nm in a first direction while the first and second semiconductor wafers are in direct physical contact with each other via the common surface, then a change of at least 10?18 F in capacitance of a first capacitor comprising the first and second capacitive coupling structures results. The first direction is essentially parallel to the common surface.
    Type: Application
    Filed: November 8, 2006
    Publication date: June 14, 2007
    Inventors: Timothy Dalton, Jeffrey Gambino, Mark Jaffe, Stephen Luce, Edmund Sprogis
  • Publication number: 20060163706
    Abstract: A method for connecting a microelectronic device to a wirebond comprises providing a substrate having a microelectronic circuit therein and forming a wiring layer over the substrate. The wiring layer includes a bilayer wiring structure comprising upper and lower electrically conductive layers separated by a protective electrically conductive layer. The lower layer of the bilayer structure is at the level of the wiring layer and the upper layer of the bilayer structure extends above the level of the wiring layer. The bilayer wiring structure is formed by depositing the upper and lower electrically conductive layers separated by a protective electrically conductive layer over the substrate, etching the upper electrically conductive layer and a portion of the protective electrically conductive layer, and thereafter separately etching the lower electrically conductive layer to form the wiring layer over the substrate. The method also includes connecting a wirebond to the upper layer of the bilayer structure.
    Type: Application
    Filed: January 25, 2005
    Publication date: July 27, 2006
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen Luce, Thomas McDevitt, Anthony Stamper
  • Publication number: 20060099775
    Abstract: A crack stop for low K dielectric materials of an integrated circuit (IC) formed on an IC chip using metal interconnects which do not form a self-passivating oxide layer, such as copper or silver interconnects, in a low-K dielectric material to prevent damage to the active area of the IC chip caused by chipping and cracking formed along peripheral edges of the IC chip during a dicing operation. A moisture barrier or edge seal is formed as a metal stack positioned along the outer peripheral edges of the active area of the IC chip. The crack stop is formed by at least one trench or groove positioned outside of the moisture barrier/edge seal on the outer periphery of the IC chip.
    Type: Application
    Filed: December 22, 2005
    Publication date: May 11, 2006
    Applicant: International Business Machines Corporation
    Inventors: Timothy Daubenspeck, Jeffrey Gambino, Stephen Luce, Thomas McDevitt, William Motsiff, Mark Pouliot, Jennifer Robbins
  • Publication number: 20060027929
    Abstract: Methods and structures having pore-closing layers for closing exposed pores in a patterned porous low-k dielectric layer, and optionally a reactive liner on the low-k dielectric. A first reactant is absorbed or retained in exposed pores in the patterned dielectric layer and then a second reactant is introduced into openings such that it enters the exposed-pores, while first reactant molecules are simultaneously being outgassed. The second reactant reacts in-situ with the outgassed first reactant molecules at a mouth region of the exposed pores to form the pore-closing layer across the mouth region of exposed pores, while retaining a portion of each pore's porosity to maintain characteristics and properties of the porous low-k dielectric layer. Optionally, the first reactant may be adsorbed onto the low-k dielectric such that upon introduction of the second reactant Into the patterned dielectric openings, a reactive liner is also formed on the low-k dielectric.
    Type: Application
    Filed: October 11, 2005
    Publication date: February 9, 2006
    Inventors: Edward Cooney, John Fitzsimmons, Jeffrey Gambino, Stephen Luce, Thomas McDevitt, Lee Nicholson, Anthony Stamper
  • Publication number: 20050266698
    Abstract: Methods and structures having pore-closing layers for closing exposed pores in a patterned porous low-k dielectric layer, and optionally a reactive liner on the low-k dielectric. A first reactant is absorbed or retained in exposed pores in the patterned dielectric layer and then a second reactant is introduced into openings such that it enters the exposed pores, while first reactant molecules are simultaneously being outgassed. The second reactant reacts in-situ with the outgassed first reactant molecules at a mouth region of the exposed pores to form the pore-closing layer across the mouth region of exposed pores, while retaining a portion of each pore's porosity to maintain characteristics and properties of the porous low-k dielectric layer. Optionally, the first reactant may be adsorbed onto the low-k dielectric such that upon introduction of the second reactant into the patterned dielectric openings, a reactive liner is also formed on the low-k dielectric.
    Type: Application
    Filed: May 26, 2004
    Publication date: December 1, 2005
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Edward Cooney, John Fitzsimmons, Jeffrey Gambino, Stephen Luce, Thomas McDevitt, Lee Nicholson, Anthony Stamper
  • Publication number: 20050242439
    Abstract: A structure (and method) for an electronic chip, includes a first circuit design module having a first grid and a second circuit design module having a second grid. The first grid and the second grid are interconnected in a fabrication layer no later than a first metallization layer that accumulates a charge during a plasma process in the fabrication.
    Type: Application
    Filed: April 28, 2004
    Publication date: November 3, 2005
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kenneth DeVries, Jeffrey Gambino, Stephen Luce, James Warnock, Francis White
  • Publication number: 20050026397
    Abstract: A crack stop for low K dielectric materials of an integrated circuit (IC) formed on an IC chip using metal interconnects which do not form a self-passivating oxide layer, such as copper or silver interconnects, in a low-K dielectric material to prevent damage to the active area of the IC chip caused by chipping and cracking formed along peripheral edges of the IC chip during a dicing operation. A moisture barrier or edge seal is formed as a metal stack positioned along the outer peripheral edges of the active area of the IC chip. The crack stop is formed by at least one trench or groove positioned outside of the moisture barrier/edge seal on the outer periphery of the IC chip.
    Type: Application
    Filed: July 28, 2003
    Publication date: February 3, 2005
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Timothy Daubenspeck, Jeffrey Gambino, Stephen Luce, Thomas McDevitt, William Motsiff, Mark Pouliot, Jennifer Robbins
  • Patent number: D475414
    Type: Grant
    Filed: May 6, 2002
    Date of Patent: June 3, 2003
    Assignee: USA Technologies, Inc.
    Inventors: H. Brock Kolls, Stephen Luce, Barry J. Patrizzi
  • Patent number: D475750
    Type: Grant
    Filed: September 5, 2001
    Date of Patent: June 10, 2003
    Assignee: USA Technologies, Inc.
    Inventors: H. Brock Kolls, Stephen Luce, Barry J. Patrizzi
  • Patent number: D475751
    Type: Grant
    Filed: September 5, 2001
    Date of Patent: June 10, 2003
    Assignee: USA Technologies, Inc.
    Inventors: H. Brock Kolls, Stephen Luce, Barry J. Patrizzi
  • Patent number: D476036
    Type: Grant
    Filed: September 5, 2001
    Date of Patent: June 17, 2003
    Assignee: USA Technologies, Inc.
    Inventors: H. Brock Kolls, Stephen Luce, Barry J. Patrizzi
  • Patent number: D476037
    Type: Grant
    Filed: May 6, 2002
    Date of Patent: June 17, 2003
    Assignee: USA Technologies, Inc.
    Inventors: H. Brock Kolls, Stephen Luce, Barry J. Patrizzi
  • Patent number: D477030
    Type: Grant
    Filed: September 24, 2002
    Date of Patent: July 8, 2003
    Assignee: USA Technologies, Inc.
    Inventors: H. Brock Kolls, Stephen Luce, Barry J. Patrizzi
  • Patent number: D478577
    Type: Grant
    Filed: February 12, 2002
    Date of Patent: August 19, 2003
    Assignee: USA Technologies, Inc.
    Inventors: H. Brock Kolls, Stephen Luce, Barry J. Patrizzi
  • Patent number: D480948
    Type: Grant
    Filed: September 20, 2002
    Date of Patent: October 21, 2003
    Assignee: USA Technologies, Inc.
    Inventors: Barry J. Patrizzi, H. Brock Kolls, Stephen Luce
  • Patent number: PP29792
    Abstract: A new and distinct cultivar of seedless table grape (Vitis sp.) named ‘NY98.0228.02’ is described. This new and distinct cultivar is particularly characterized by its large berry size, seedlessness, and berry flavor.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: November 6, 2018
    Assignee: CORNELL UNIVERSITY
    Inventors: Bruce Reisch, R. Stephen Luce