Abstract: The present invention relates to a card reader assembly. The card reader assembly can be mounted in a variety of vending equipment, arcade game equipment, and other suitable equipment. Furthermore, the card reader assembly can be mounted in a standard size vending machine bill validator opening. The card reader assembly can provide for the optional mounting of a card reader, a card reader interface circuit board, a payment module board, a communication board, and or a printer. The printer mechanism is mounted on a printer bracket. The printer bracket can be slid over the edges of and fastened to the support bracket. A paper exit slot can be provided in the card reader assembly faceplate to allow the printer paper to exit through the faceplate such that a user can receive the printer paper. In addition, the printer mechanism, card reader, and or a pushbutton can be electrically connected to the card reader interface board.

Abstract: An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip to backside metallurgy on the imaging chip. The backside metallurgy of the imaging chip is connected to metallurgy on the active surface of the logic chip using an array of solder bumps in BGA fashion. The interconnection arrangement provides a CSP which matches the space constraints of a cell phone, for example. The arrangement also utilizes minimal wire lengths for reduced noise. Connection of the CSP to a carrier package may be either by conductive through vias or wire bonding. The CSP is such that the imaging chip may readily be mounted across an aperture in the wall of a cell phone, for example, so as to expose the light sensitive pixels on the active surface of said imaging chip to light.

Abstract: A crack stop for low K dielectric materials of an integrated circuit (IC) formed on an IC chip using metal interconnects which do not form a self-passivating oxide layer, such as copper or silver interconnects, in a low-K dielectric material to prevent damage to the active area of the IC chip caused by chipping and cracking formed along peripheral edges of the IC chip during a dicing operation. A moisture barrier or edge seal is formed as a metal stack positioned along the outer peripheral edges of the active area of the IC chip. The crack stop is formed by at least one trench or groove positioned outside of the moisture barrier/edge seal on the outer periphery of the IC chip.

Abstract: Structures for aligning wafers and methods for operating the same. The structure includes (a) a first semiconductor wafer including a first capacitive coupling structure, and (b) a second semiconductor wafer including a second capacitive coupling structure. The first and second semiconductor wafers are in direct physical contact with each other via a common surface. If the first and second semiconductor wafers are moved with respect to each other by a first displacement distance of 1 nm in a first direction while the first and second semiconductor wafers are in direct physical contact with each other via the common surface, then a change of at least 10?18 F in capacitance of a first capacitor comprising the first and second capacitive coupling structures results. The first direction is essentially parallel to the common surface.

Abstract: A method for connecting a microelectronic device to a wirebond comprises providing a substrate having a microelectronic circuit therein and forming a wiring layer over the substrate. The wiring layer includes a bilayer wiring structure comprising upper and lower electrically conductive layers separated by a protective electrically conductive layer. The lower layer of the bilayer structure is at the level of the wiring layer and the upper layer of the bilayer structure extends above the level of the wiring layer. The bilayer wiring structure is formed by depositing the upper and lower electrically conductive layers separated by a protective electrically conductive layer over the substrate, etching the upper electrically conductive layer and a portion of the protective electrically conductive layer, and thereafter separately etching the lower electrically conductive layer to form the wiring layer over the substrate. The method also includes connecting a wirebond to the upper layer of the bilayer structure.

Abstract: A crack stop for low K dielectric materials of an integrated circuit (IC) formed on an IC chip using metal interconnects which do not form a self-passivating oxide layer, such as copper or silver interconnects, in a low-K dielectric material to prevent damage to the active area of the IC chip caused by chipping and cracking formed along peripheral edges of the IC chip during a dicing operation. A moisture barrier or edge seal is formed as a metal stack positioned along the outer peripheral edges of the active area of the IC chip. The crack stop is formed by at least one trench or groove positioned outside of the moisture barrier/edge seal on the outer periphery of the IC chip.

Abstract: Methods and structures having pore-closing layers for closing exposed pores in a patterned porous low-k dielectric layer, and optionally a reactive liner on the low-k dielectric. A first reactant is absorbed or retained in exposed pores in the patterned dielectric layer and then a second reactant is introduced into openings such that it enters the exposed-pores, while first reactant molecules are simultaneously being outgassed. The second reactant reacts in-situ with the outgassed first reactant molecules at a mouth region of the exposed pores to form the pore-closing layer across the mouth region of exposed pores, while retaining a portion of each pore's porosity to maintain characteristics and properties of the porous low-k dielectric layer. Optionally, the first reactant may be adsorbed onto the low-k dielectric such that upon introduction of the second reactant Into the patterned dielectric openings, a reactive liner is also formed on the low-k dielectric.

Abstract: Methods and structures having pore-closing layers for closing exposed pores in a patterned porous low-k dielectric layer, and optionally a reactive liner on the low-k dielectric. A first reactant is absorbed or retained in exposed pores in the patterned dielectric layer and then a second reactant is introduced into openings such that it enters the exposed pores, while first reactant molecules are simultaneously being outgassed. The second reactant reacts in-situ with the outgassed first reactant molecules at a mouth region of the exposed pores to form the pore-closing layer across the mouth region of exposed pores, while retaining a portion of each pore's porosity to maintain characteristics and properties of the porous low-k dielectric layer. Optionally, the first reactant may be adsorbed onto the low-k dielectric such that upon introduction of the second reactant into the patterned dielectric openings, a reactive liner is also formed on the low-k dielectric.

Abstract: A structure (and method) for an electronic chip, includes a first circuit design module having a first grid and a second circuit design module having a second grid. The first grid and the second grid are interconnected in a fabrication layer no later than a first metallization layer that accumulates a charge during a plasma process in the fabrication.

Abstract: A crack stop for low K dielectric materials of an integrated circuit (IC) formed on an IC chip using metal interconnects which do not form a self-passivating oxide layer, such as copper or silver interconnects, in a low-K dielectric material to prevent damage to the active area of the IC chip caused by chipping and cracking formed along peripheral edges of the IC chip during a dicing operation. A moisture barrier or edge seal is formed as a metal stack positioned along the outer peripheral edges of the active area of the IC chip. The crack stop is formed by at least one trench or groove positioned outside of the moisture barrier/edge seal on the outer periphery of the IC chip.

Abstract: A new and distinct cultivar of seedless table grape (Vitis sp.) named ‘NY98.0228.02’ is described. This new and distinct cultivar is particularly characterized by its large berry size, seedlessness, and berry flavor.

Abstract: The invention is a new and distinct variety of grapevine plant named ‘ARAVELLE’, which is characterized by its adaptability to the Finger Lakes grape production region of New York and similar regions; fruit suitable for production of wines; moderate resistance to downy and powdery mildews; and resistance to Botrytis bunch rot.