Patents by Inventor Stephen M. Douglass
Stephen M. Douglass has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7539848Abstract: A system is disclosed comprising a logic circuit in an integrated circuit device, wherein the logic circuit comprises a logic fabric that includes a plurality of configurable logic blocks, switching blocks, and input/output blocks, wherein the logic fabric is configured according to configuration data provided to the integrated circuit device from an external memory and at least a portion of the logic fabric is configured as a configured processor to perform a first fixed logic function according to the configuration data. A fixed logic processor, a first auxiliary processing interface, a second fixed logic processor, a second auxiliary processing interface enable communication with the configured processor, wherein the configured processor remains configured to enable both the fixed logic processor and the second fixed logic processor to access the configured processor to perform the fixed logic function.Type: GrantFiled: September 30, 2005Date of Patent: May 26, 2009Assignee: Xilinx, Inc.Inventors: Stephen M. Douglass, Ahmad R. Ansari
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Patent number: 7420392Abstract: Interconnecting logic provides connectivity of an embedded fixed logic circuit, or circuits, with programmable logic fabric of a programmable gate array such that the fixed logic circuit functions as an extension of the programmable logic fabric. The interconnecting logic includes interconnecting tiles and may further include interfacing logic. The interconnecting tiles provide selective connectivity between inputs and/or outputs of the fixed logic circuit and interconnect of the programmable logic fabric. The interfacing logic, when included, provides logic circuitry that conditions data transfers between the fixed logic circuit and the programmable logic fabric. In one operation, the programmable logic fabric is configured prior to the startup/boot sequence of the fixed logic circuit. In another operation, the fixed logic circuit is started up and is employed to configure the programmable logic fabric.Type: GrantFiled: July 23, 2004Date of Patent: September 2, 2008Assignee: XILINX, Inc.Inventors: David P. Schultz, Stephen M. Douglass, Steven P. Young, Nigel G. Herron, Mehul R. Vashi, Jane W. Sowards
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Patent number: 7406670Abstract: Method and apparatus for generating a test program for an integrated circuit having an embedded processor. One embodiment has a system which includes an embedded microprocessor; a plurality of assembly language instructions stored in a memory, where the assembly language instructions substantially exercise a critical path or a path closest to the critical path in the embedded microprocessor; and programmable test circuitry having a programmable clock circuit for providing a multiplied clock signal to the embedded microprocessor in order to execute the assembly language instructions.Type: GrantFiled: August 1, 2007Date of Patent: July 29, 2008Assignee: Xilinx, Inc.Inventors: Ahmad R. Ansari, Mehul R. Vashi, Nigel G. Herron, Stephen M. Douglass
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Patent number: 7269805Abstract: Method and apparatus for generating a test program for an integrated circuit having an embedded processor. One embodiment has a system which includes an embedded microprocessor; a plurality of assembly language instructions stored in a memory, where the assembly language instructions substantially exercise a critical path or a path closest to the critical path in the embedded microprocessor; and programmable test circuitry having a programmable clock circuit for providing a multiplied clock signal to the embedded microprocessor in order to execute the assembly language instructions.Type: GrantFiled: April 30, 2004Date of Patent: September 11, 2007Assignee: Xilinx, Inc.Inventors: Ahmad R. Ansari, Mehul R. Vashi, Nigel G. Herron, Stephen M. Douglass
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Patent number: 7231621Abstract: Method and apparatus for generating a test program for a programmable logic device having an embedded processor. Predetermined code is obtained to exercise at least one speed limiting path identified. To the predetermined code is added wrapper code to provide the test program, the wrapper code in part for loading the predetermined code into cache of the embedded processor for testing the at least one speed limiting path of the embedded processor identified.Type: GrantFiled: April 30, 2004Date of Patent: June 12, 2007Assignees: Xilinx, Inc., International Business MachinesInventors: Nigel G. Herron, Ahmad R. Ansari, Stephen M. Douglass, Anthony Correale, Jr., Leslie M. DeBruyne
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Patent number: 7194600Abstract: A method and apparatus for processing data within a programmable gate array comprise a first fixed logic processor and a second fixed logic processor that are embedded within the programmable gate array and detect a custom operation code. The processing continues when a fixed logic processor provides an indication of the custom operational code to the programmable gate array. The processing continues by having at least a portion of the programmable gate array, which is configured as a dedicated processor, performing a fixed logic routine upon receiving the indication from the fixed logic processor.Type: GrantFiled: February 17, 2005Date of Patent: March 20, 2007Assignee: Xilinx, Inc.Inventors: Stephen M. Douglass, Ahmad R. Ansari
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Patent number: 6961919Abstract: A method for designing an integrated circuit having both fixed logic and programmable logic components. An intended set of applications for the integrated circuit is first identified. In addition, for each of the intended set of applications, the logic requirements are identified. An approximate number of configurable logic blocks and at least one fixed logic circuit are selected that, when combined to operate cooperatively, meet a substantial portion of the logic requirements and the logic functions of the intended set of applications. The method also involves designing the integrated circuit with the approximate number of configurable logic blocks arranged and interconnected to form a fabric that surrounds an opening, and inserting the at least one fixed logic circuit into the opening in the fabric. In addition, the method involves adding logic to the integrated circuit that interfaces the at least one fixed logic circuit to the fabric and input/output circuitry.Type: GrantFiled: March 4, 2002Date of Patent: November 1, 2005Assignee: Xilinx, Inc.Inventor: Stephen M. Douglass
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Patent number: 6886092Abstract: A method and apparatus for processing data within a programmable gate array begins when a fixed logic processor that is embedded within the programmable gate array detects a custom operation code. The processing continues when the fixed logic processor provides an indication of the custom operational code to the programmable gate array. The processing continues by having at least a portion of the programmable gate array, which is configured as a dedicated processor, performing a fixed logic routine upon receiving the indication from the fixed logic processor.Type: GrantFiled: November 19, 2001Date of Patent: April 26, 2005Assignee: Xilinx, Inc.Inventors: Stephen M. Douglass, Ahmad R. Ansari
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Patent number: 6798239Abstract: Interconnecting logic provides connectivity of an embedded fixed logic circuit, or circuits, with programmable logic fabric of a programmable gate array such that the fixed logic circuit functions as an extension of the programmable logic fabric. The interconnecting logic includes interconnecting tiles and may further include interfacing logic. The interconnecting tiles provide selective connectivity between inputs and/or outputs of the fixed logic circuit and the interconnects of the programmable logic fabric. The interfacing logic, when included, provides logic circuitry that conditions data transfers between the fixed logic circuit and the programmable logic fabric.Type: GrantFiled: September 28, 2001Date of Patent: September 28, 2004Assignee: Xilinx, Inc.Inventors: Stephen M. Douglass, Steven P. Young, Nigel G. Herron, Mehul R. Vashi, Jane W. Sowards
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Patent number: 6693452Abstract: Interconnecting logic provides connectivity of an embedded fixed logic circuit, or circuits, with programmable logic fabric of a programmable gate array such that the fixed logic circuit functions as an extension of the programmable logic fabric. The interconnecting logic includes interconnecting tiles and may further include interconnecting logic. The interconnecting tiles provide selective connectivity between inputs and/or outputs of the fixed logic circuit and the interconnects of the programmable logic fabric. The interconnecting logic, when included, provides logic circuitry that conditions data transfers between the fixed logic circuit and the programmable logic fabric. The invention is directed towards the various needs and requirements of the layout and floor planning of a device having both fixed logic circuitry and programmable logic circuitry.Type: GrantFiled: February 25, 2002Date of Patent: February 17, 2004Assignee: Xilinx, Inc.Inventors: Ahmad R. Ansari, Stephen M. Douglass
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Patent number: 6662285Abstract: A data processing system having a user configurable memory controller, one or more local block RAMs, one or more global block RAMs and a processor core can be configured in a single field programmable gate array (FPGA). The address depth of the global block RAMs and the number of wait states can be selected by a user, and they can be set either prior to configuration of the FPGA or programmed using instructions of the processor core. The number of wait states of the local block RAM is also user selectable. An algorithm that can optimize the address depth and the number of wait states to achieve a performance level is also disclosed. The present invention can be applied to designs having separate instruction and data sides.Type: GrantFiled: July 27, 2001Date of Patent: December 9, 2003Assignee: Xilinx, Inc.Inventors: Stephen M. Douglass, Prasad L. Sastry, Mehul R. Vashi, Robert Yin
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Publication number: 20030062922Abstract: Interconnecting logic provides connectivity of an embedded fixed logic circuit, or circuits, with programmable logic fabric of a programmable gate array such that the fixed logic circuit functions as an extension of the programmable logic fabric. The interconnecting logic includes interconnecting tiles and may further include interfacing logic. The interconnecting tiles provide selective connectivity between inputs and/or outputs of the fixed logic circuit and the interconnects of the programmable logic fabric. The interfacing logic, when included, provides logic circuitry that conditions data transfers between the fixed logic circuit and the programmable logic fabric.Type: ApplicationFiled: September 28, 2001Publication date: April 3, 2003Applicant: Xilinx, Inc.Inventors: Stephen M. Douglass, Steven P. Young
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Patent number: 6522167Abstract: A data processing system having a user configurable memory controller, one or more block RAMS, and a processor core can be configured in a single field programmable gate array (FPGA). The address depth of the block RAMs and the number of wait states can be selected by a user, and they can be set either prior to configuration of the FPGA or programmed using instructions of the processor core. An algorithm that can optimize the address depth and the number of wait states to achieve a performance level is also disclosed. The present invention can be applied to designs having separate instruction and data sides.Type: GrantFiled: January 9, 2001Date of Patent: February 18, 2003Assignee: Xilinx, Inc.Inventors: Ahmad R. Ansari, Stephen M. Douglass, Mehul R. Vashi, Steven P. Young
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Patent number: 6243664Abstract: Methods for designing a programmable interconnect matrix having reduced connectivity to achieve maximum routability for the reduced connectivity. An array of multiplexors, each having a multiplexor width wmux that is less than number of input conductors for the programmable matrix, are coupled to the input conductors of the programmable interconnect matrix such that the number of input signals shared between any two multiplexors is less than the multiplexor width wmux and such that each input signal has approximately the same number of chances to route. To better ensure the successful routing of input signals by a programmable interconnect matrix designed according to the present methods, improved routing methods are also described. According to a first embodiment, routing is accomplished by swapping successfully routed input signals with a blocked input signal and determining whether the input signal that has been swapped out may be routed through available multiplexors.Type: GrantFiled: October 27, 1998Date of Patent: June 5, 2001Assignee: Cypress Semiconductor CorporationInventors: Hagop A. Nazarian, Stephen M. Douglass, W. Alfred Graf, S. Babar Raza, Sundar Rajan, Shiva Sorooshian Borzin, Darren Neuman
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Patent number: 5923868Abstract: Methods for designing a programmable interconnect matrix having reduced connectivity to achieve maximum routability for the reduced connectivity. An array of multiplexors, each having a multiplexor width w.sub.mux that is less than number of input conductors for the programmable matrix, are coupled to the input conductors of the programmable interconnect matrix such that the number of input signals shared between any two multiplexors is less than the multiplexor width w.sub.mux and such that each input signal has approximately the same number of chances to route. To better ensure the successful routing of input signals by a programmable interconnect matrix designed according to the present methods, improved routing methods are also described. According to a first embodiment, routing is accomplished by swapping successfully routed input signals with a blocked input signal and determining whether the input signal that has been swapped out may be routed through available multiplexors.Type: GrantFiled: October 23, 1997Date of Patent: July 13, 1999Assignee: Cypress Semiconductor Corp.Inventors: Hagop A. Nazarian, Stephen M. Douglass, W. Alfred Graf, S. Babar Raza, Sundar Rajan, Shiva Sorooshian Borzin, Darren Newman
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Patent number: 5848066Abstract: Methods for designing a programmable interconnect matrix having reduced connectivity to achieve maximum routability for the reduced connectivity. An array of multiplexors, each having a multiplexor width w.sub.mux that is less than number of input conductors for the programmable matrix, are coupled to the input conductors of the programmable interconnect matrix such that the number of input signals shared between any two multiplexors is less than the multiplexor width w.sub.mux and such that each input signal has approximately the same number of chances to route. To better ensure the successful routing of input signals by a programmable interconnect matrix designed according to the present methods, improved routing methods are also described. According to a first embodiment, routing is accomplished by swapping successfully routed input signals with a blocked input signal and determining whether the input signal that has been swapped out may be routed through available multiplexors.Type: GrantFiled: August 30, 1996Date of Patent: December 8, 1998Assignee: Cypress Semiconductor Corp.Inventors: Hagop A. Nazarian, Stephen M. Douglass, W. Alfred Graf, S. Babar Raza, Sundar Rajan, Shiva Sorooshian Borzin, Darren Neuman
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Patent number: 5701092Abstract: An OR array including a first multiplicity of OR devices, to which a second multiplicity of product term signals are variably distributed. Some product term signals are distributed to four OR devices, other product term signals are distributed two or three OR devices, and still other product term signals are distributed to only one OR device.Type: GrantFiled: July 28, 1995Date of Patent: December 23, 1997Assignee: Cypress Semiconductor Corp.Inventors: Norman P. Taffe, Stephen M. Douglass, Hagop Nazarian
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Patent number: 5689686Abstract: Methods for designing a programmable interconnect matrix having reduced connectivity to achieve maximum routability for the reduced connectivity. An array of multiplexors, each having a multiplexor width w.sub.mux that is less than number of input conductors for the programmable matrix, are coupled to the input conductors of the programmable interconnect matrix such that the number of input signals shared between any two multiplexors is less than the multiplexor width w.sub.mux and such that each input signal has approximately the same number of chances to route. To better ensure the successful routing of input signals by a programmable interconnect matrix designed according to the present methods, improved routing methods are also described. According to a first embodiment, routing is accomplished by swapping successfully routed input signals with a blocked input signal and determining whether the input signal that has been swapped out may be routed through available multiplexors.Type: GrantFiled: March 21, 1997Date of Patent: November 18, 1997Assignee: Cypress Semiconductor Corp.Inventors: Hagop A. Nazarian, Stephen M. Douglass, W. Alfred Graf, S. Babar Raza, Sundar Rajan, Shiva Sorooshian Borzin, Darren Neuman
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Patent number: 5621338Abstract: A user configurable circuit contains clock logic, a switching element and a data path circuit. Input data is received in the switching element, and the switching element and the data path circuit constitute the entire data path for the circuit. A plurality of user configurable inputs are received to configure the circuit for a particular user application. The clock logic and the switching element implement a logic function that is configurable by the user configurable inputs. The logic function is pre-processed in the clock logic so that minimal delay occurs in the data path. In addition, the propagation delay through the switching element and the register is independent of the user configurable inputs. The user configurable circuit of the present invention has application for use as a macro cell for a programmable logic device permitting the user to configure the circuit as a D-type flip-flop, a T-type flip-flop. In addition, the user selects the polarity for the output circuit.Type: GrantFiled: January 11, 1996Date of Patent: April 15, 1997Assignee: Cypress Semiconductor Corp.Inventors: Lin-Shih Liu, Syed B. Raza, Hagop Nazarian, George M. Ansel, Stephen M. Douglass, Jeffery S. Hunt
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Patent number: RE37577Abstract: A user configurable circuit contains clock logic, a switching element and a data path circuit. Input data is received in the switching element, and the switching element and the data path circuit constitute the entire data path for the circuit. A plurality of user configurable inputs are received to configure the circuit for a particular user application. The clock logic and the switching element implement a logic function that is configurable by the user configurable inputs. The logic function is pre-processed in the clock logic so that minimal delay occurs in the data path. In addition, the propagation delay through the switching element and the register is independent of the user configurable inputs. The user configurable circuit of the present invention has application for use as a macro cell for a programmable logic device permitting the user to configure the circuit as a D-type flip-flop, a T-type flip-flop. In addition, the user selects the polarity for the output circuit.Type: GrantFiled: March 24, 1998Date of Patent: March 12, 2002Assignee: Cypress Semiconductor CorporationInventors: Lin-Shih Liu, Syed Babar Raza, Hagop Nazarian, George M. Ansel, Stephen M. Douglass, Jeffrey Scott Hunt