Patents by Inventor Stephen M. Prather

Stephen M. Prather has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7826581
    Abstract: An apparatus and method are disclosed synchronization of a clock signal to a data signal. The apparatus includes a phase lock and tracking logic circuit configured to detect a plurality of values. Each of the plurality of values indicates a position of a data edge of the data signal. The phase lock and tracking logic circuit adds the plurality of values to generate a result and to adjust the clock signal if the result is greater than a predetermined value, or threshold. The phase lock and tracking logic circuit may be configured to maintain the clock signal linearity approximately between the end of a first data packet and the beginning of a second data packet.
    Type: Grant
    Filed: October 5, 2004
    Date of Patent: November 2, 2010
    Assignee: Cypress Semiconductor Corporation
    Inventors: Stephen M. Prather, Matthew S. Berzins, Charles A. Cornell, Steven P. Larky, Joseph A. Cetin
  • Patent number: 7394293
    Abstract: Output driver circuits and related methods. In one example, the output driver circuit includes a translator for converting the single ended data input signal into a pair of signals; a set of output transistors selectively controlled by the pair of signals; a cascode current source for providing a substantially constant current to the set of output transistors when the output transistors are active; and a dump path in parallel with the set of output transistors. A circuit portion for pre-charging the pair of signals to a pre-charged voltage between VCC and ground may also be provided.
    Type: Grant
    Filed: November 23, 2005
    Date of Patent: July 1, 2008
    Assignee: Cypress Semiconductor Corp.
    Inventors: Jeffrey Waldrip, Stephen M. Prather, Matthew Berzins, Charles Cornell
  • Patent number: 7239178
    Abstract: A voltage level translation circuit includes a first power supply voltage, a second power supply voltage, wherein the second supply voltage is lower than the first supply voltage, a low voltage input, wherein the low voltage input is referenced from the second supply voltage, a resistive element leaker transistor having a source and a drain, wherein the source is coupled to the first power supply voltage, a PMOSFET having a gate and a source, wherein the source is coupled to the first power supply voltage, and a pulse generator coupled to the gate of the PMOSFET, wherein the pulse generator is capable of controlling the operation of the PMOSFET.
    Type: Grant
    Filed: March 23, 2005
    Date of Patent: July 3, 2007
    Assignee: Cypress Semiconductor Corp.
    Inventors: Charles A. Cornell, Matthew S. Berzins, Stephen M. Prather
  • Patent number: 7176720
    Abstract: Disclosed is a circuit comprising a differential input amplifier stage, a capacitor stage, an inverter chain stage, and a biasing circuit. The inverter chain stage may be formed with or without feedback depending on whether a clock signal or data signal is to be translated using the disclosed circuit. The biasing circuit can be formed using either inverters or transmission gates. Moreover, the biasing circuit, the inverter chain stage, and the amplifier stage can be connected to a power down circuit which, when the translator is not being used, will ensure various circuitry of the translator will not consume extensive power. The inverter chain stage, biasing circuit, and capacitor stage are formed on both an upper and lower section to produce true and complementary outputs that have a consistent and equal delay from the transitions of the incoming differential input signal so as to minimize jitter and associated duty cycle of the translated output.
    Type: Grant
    Filed: March 11, 2004
    Date of Patent: February 13, 2007
    Assignee: Cypress Semiconductor Corp.
    Inventors: Stephen M. Prather, Jeffrey F. Waldrip, Matthew S. Berzins, Charles A. Cornell
  • Patent number: 7173453
    Abstract: A circuit according to some embodiments of the invention includes a first differential to single ended translator having a first output, a second differential to single ended translator having a second output, and a latch coupled to the first output and the second output, where the latch is configured to select the slower of the first output and the second output.
    Type: Grant
    Filed: December 17, 2004
    Date of Patent: February 6, 2007
    Assignee: Cypress Semiconductor Corp.
    Inventors: Stephen M. Prather, Matthew S. Berzins, Jeffrey W. Waldrip
  • Patent number: 6781465
    Abstract: Embodiments of the invention describe a method and apparatus for detecting valid differential signals with half the number of differential amplifiers required by conventional methods. By purposely mismatching an otherwise matched differential pair, a self-induced DC offset voltage is created and the additional circuitry required to generate external reference voltages according to conventional methods is eliminated. Embodiments of the invention also have improved noise rejection characteristics and enhanced high-speed capability compared to conventional circuits.
    Type: Grant
    Filed: December 13, 2002
    Date of Patent: August 24, 2004
    Assignee: Cypress Semiconductor Corp.
    Inventors: Matthew S. Berzins, Charles A. Cornell, Stephen M. Prather